LTC692(Rev0) Ver la hoja de datos (PDF) - Linear Technology
Número de pieza
componentes Descripción
Fabricante
LTC692 Datasheet PDF : 16 Pages
| |||
LTC692/LTC693
APPLICATI S I FOR ATIO
If battery connections are made through long wires, a 10Ω
to 100Ω series resistor and a 0.1µF capacitor are recom-
mended to prevent any overshoot beyond VCC due to the
lead inductance (Figure 4).
10Ω
3.9M
VBATT
0.1µF
LTC692
LTC693
GND
LTC692/3 • F04
alternative signal to drive the CE, CS, or Write input of
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM or
NOVRAM to achieve similar protection. Figure 5 shows the
timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor's address
decoder output. Figure 6 shows a typical nonvolatile
CMOS RAM application.
Memory protection can also be achieved with the LTC692
by using RESET as shown in Figure 7.
Figure 4. 10Ω/0.1µF combination eliminates inductive
overshoot and prevents spurious resets during battery
replacement.
Table 1 shows the state of each pin during battery backup.
When the battery switchover section is not used, connect
VBATT to GND and VOUT to VCC.
Memory Protection
The LTC693 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when VCC is at an invalid level. Two
additional pins, CE IN and CE OUT, control the Chip Enable
or Write inputs of CMOS RAM. When VCC is 5V, CE OUT
follows CE IN with a typical propagation delay of 20ns.
When VCC falls below the reset voltage threshold or VBATT,
CE OUT is forced high, independent of CE IN. CE OUT is an
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL STATUS
VCC
VOUT
VBATT
BATT ON
PFI
C2 monitors VCC for active switchover.
VOUT is connected to VBATT through an internal PMOS switch.
The supply current is 1µA maximum.
Logic high. The open-circuit output voltage is equal to VOUT.
Power Failure Input is ignored.
PFO
Logic low
RESET Logic low
RESET Logic high. The open-circuit output voltage is equal to VOUT.
LOW LINE Logic low
WDI
Watchdog Input is ignored.
WDO
CE IN
Logic high. The open-circuit output voltage is equal to VOUT.
Chip Enable Input is ignored.
CE OUT
OSC IN
Logic high. The open-circuit output voltage is equal to VOUT.
OSC IN is ignored.
OSC SEL OSC SEL is ignored.
VCC
CE IN
V2
V1
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CE OUT
VOUT = VBATT
10
Figure 5. Timing Diagram for CE IN and CE OUT
VOUT = VBATT
LTC692/3 • F05
Share Link: 