MAX697 Ver la hoja de datos (PDF) - Maxim Integrated
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MAX697 Datasheet PDF : 16 Pages
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MAX696/MAX697
Microprocessor Supervisory Circuits
Pin Description
PIN
MAX696
MAX697
1
—
2
—
3
3
4
5
5
—
6
6
7
7
8
8
9
9
10
10
11
11
12
2
13
4
14
14
15
15
16
16
NAME
FUNCTION
VBATT
VOUT
VCC
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
PFI
PFO
WDI
N.C.
LLIN
WDO
RESET
RESET
Backup-Battery Input. Connect to ground if a backup battery is not used.
The higher of VCC or VBATT is internally switched to VOUT. Connect VOUT to VCC if
VOUT and VBATT are not used.
+5V Input
0V Ground Reference for All Signals
BATT ON goes High when VOUT is Internally Switched to the VBATT Input. It goes
low when VOUT is internally switched to VCC. The output typically sinks 7mA and
can directly drive the base of an external pnp transistor to increase the output current
above the 50mA rating of VOUT.
LOW LINE goes Low when LLIN Falls Below 1.3V. It returns high as soon as LLIN
rises above 1.3V. See Figure 5.
OSC IN Sets the Reset Delay Timing and Watchdog Timeout Period when OSC SEL
Floats or is Driven Low. The timing can also be adjusted by connecting an external
capacitor to this pin. See Figure 7. When OSC SEL is high, OSC IN selects between
fast and slow watchdog timeout periods
When OSC SEL is Unconnected or Driven High, the Internal Oscillator Sets the
Reset Time Delay and Watchdog Timeout Period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3µA internal pullup. See
Table 1.
PFI is the Noninverting Input to the Power-Fail Comparator. When PFI is less than
1.3V, PFO goes low. Connect PFI to GND or VOUT when not used. See Figure 1.
PFO is the Output of the Power-Fail Comparator. It goes low when PFI is less than
1.3V. The comparator is turned off and PFO goes low when VCC is below VBATT.
The Watchdog Input, WDI, is a Three-Level Input. If WDI remains either high or low
for longer than the watchdog timeout period, RESET pulses low and WDO goes low.
The watchdog timer is disabled when WDI is left floating or is driven to mid-supply.
The timer resets with each transition at the watchdog timer input.
No Connection. Leave this pin open.
Low-Line Input. LLIN is the CMOS input to a comparator whose other input is a
precision 1.3V reference. The output is LOW LINE and is also connected to the reset
pulse generator. See Figure 2.
The Watchdog Output, WDO, goes Low if WDI Remains either High or Low for
Longer than the Watchdog Timeout Period. WDO is set high by the next transition at
WDI. If WDI is unconnected or at mid-supply, WDO remains high. WDO also goes
high when LOW LINE goes low.
RESET goes Low whenever LLIN Falls Below 1.3V or VCC Falls Below the VBATT
Input Voltage. RESET remains low for 50ms after LLIN goes above 1.3V. RESET also
goes low for 50ms if the watchdog timer is enabled but not serviced within its timeout
period. The RESET pulse width can be adjusted as shown in Table 1.
RESET is an Active-High Output. It is the inverse of RESET.
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