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MAX697 Ver la hoja de datos (PDF) - Maxim Integrated

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Fabricante
MAX697
MaximIC
Maxim Integrated MaximIC
MAX697 Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
MAX696/MAX697
Microprocessor Supervisory Circuits
WATCHDOG INPUT
VCC 2.7V
+
-
+
-
1.0V
TRANSITION
DETECTOR
FOR EACH TRANSITION
LOW LINE
(HI IF LLIN < 1.3V)
HI IF WATCHDOG
INPUT IS FLOATING
PRESCALER
Q6
10.24kHz FROM INTERNAL OSCILLATOR
OR EXTERNALLY SET FREQUENCY FROM
OSC IN PIN
WATCHDOG TIMEOUT SELECT
RESET
COUNTER
R Q10/12
WATCHDOG
COUNTER
Q11
Q13
R
Q15
WATCHDOG
TIMEOUT
SELECTOR
LOGIC
GOES HIGH AT THE
END OF WATCHDOG
TIMEOUT PERIOD
S
R
RESET
FLIP FLOP
Q
Q
S
Q
R
S
LONG/SHORT
FF
R
LOW
LINE
WATCHDOG
FAULT FF
Q
RESET RESET
WATCHDOG OUTPUT
Figure 6. Watchdog Timer Block Diagram
a reset is issued. The normal timeout period becomes
effective following the first transition of WDI after RESET
has gone high. The watchdog timer is restarted at the end
of reset, whether the reset was caused by lack of activ-
ity on WDI or by LLIN falling below 1.3V. If WDI remains
either high or low, reset pulses will be issued every 1.6s.
The watchdog monitor can be deactivated by floating the
watchdog input (WDI).
The watchdog output (WDO) goes low if the watchdog
timer times out, and it remains low until set high by the
next transition on the watchdog input. WDO is also set
high when LLIN goes below 1.3V. The watchdog timeout
period defaults to 1.6s and the reset pulse width defaults
to 50ms. The MAX696 and MAX697 allow these times to
be adjusted per Table 1.
The internal oscillator is enabled when OSC SEL is high
or floating. In this mode, OSC IN selects between the
1.6s and 100ms watchdog timeout periods. In either case,
immediately after a reset, the timeout period is 1.6s. This
gives the microprocessor time to reinitialize the system.
WD transmissions while RESET is low are ignored. If OSC
IN is low, then the 100ms watchdog period becomes effec-
tive after the first transition of WDI. The software should
be written so the I/O port driving WDI is left in its power-up
reset state until the initialization routines are completed
and the microprocessor is able to toggle WDI at the mini-
mum 70ms watchdog timeout period.
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