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PTN2111

1:10 LVDS clock distribution device

Philips Electronics 

Philips Semiconductors

1:10 LVDS clock distribution device

Product Data

PTN2111

CONTROL REGISTER SPECIFICATION

The PTN2111 is provided with an 11-bit shift register with a serial-in

and a Control Register. The purpose is to enable or power-off each

output clock channel and to select the clock input. The PTN2111

provides two working modes: Programmed mode, and Standard

mode.

Programmed Mode (EN = 1)

The shift register has a serial input to load the working configuration.

Once the configuration is loaded with 11 clock pulses, another clock

pulse loads the configuration into the Control Register. To restart the

configuration of the shift register, a reset of the state machine must

be done with a clock pulse on CK, and the EN set to LOW. The

Control Register can be configured only one time after each reset.

D0 is the first bit shifted in, D10 is the last bit shifted in. Bit D0

controls Q9, D9 controls Q0, and D10 controls CLKIN.

Standard Mode (EN = 0)

In Standard Mode, the PTN2111 is not programmable. All clock

buffer outputs are enabled. The LVDS clock input is selected from

Clock0 or Clock1 with the SI pin, as shown in the Truth Table.

Table 1. Truth Table of State Machine Inputs

EN SI

CK

OUTPUT

L

L

X

All outputs enabled,

Clock0 selected,

Control Register disabled.

L

H

X

All outputs enabled,

Clock1 selected,

Control Register disabled.

H

L

First stage stores “L”, other

stages store the data of

previous stage.

H

H

First stage stores “H”, other

stages store the data of

previous stage.

L

X

Reset of the state machine,

Shift register, and Control

Register.

Table 2. Configuration of the Control Register

Control Register bit D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

Function

Q9

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0 CLK_SEL

Table 3. Truth Table of the Control Register

D10

L

H

X

X = Don’t Care

Dn[0:9]

H

H

L

AC ELECTRICAL CHARACTERISTICS (Control Register)

SYMBOL

PARAMETER

CONDITIONS

fMAX

ts

th

trem

tw

Maximum frequency of shift register

Clock to SI setup time

Clock to SI hold time

Enable to clock removal time

Minimum clock pulse width

Qn[0:9]

Clock0

Clock1

Qn output disabled

MIN

TYP

MAX

UNIT

50

MHz

4.0

ns

1.0

ns

4.0

ns

5

ns

2001 Jun 19

6

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