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A8437

Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver

Allegro MicroSystems 

A8437

Mobile Phone Xenon Photoflash Capacitor Charger

with IGBT Driver

Application Information

General Operation Overview

T = R × C × ln (V0 / VT) .

(1)

The CHARGE pin enables the part and starts charging.

The ¯D¯¯¯¯O¯¯¯N¯¯E¯ open-drain indicator is pulled low when

CHARGE is high and target output voltage is reached.

Charging is reinitiated when the REG pin voltage falls

below the regulation threshold. Pulling the CHARGE

pin low stops charging and forces the chip into low-

power standby mode.

Output Voltage Regulation

When the REG pin is connected to VIN, the A8437

stops charging the output voltage after the reflected

voltage (VSW – VIN) reaches 31.5 V. In this mode,

charging can be reinitiated by cycling the CHARGE

signal through a low to high transition.

The A8437 can also be used to regulate output voltage

within a predetermined window. In this mode, con-

nect a capacitor, CREG, and resistor, RREG, from the

REG pin to GND (refer to the figure Application 3).

When CHARGE is held high, the voltage monitoring

circuit of the A8437 is always active, irrespective of

the REG pin voltage level.

Voltage Regulation Using Predicitive Droop The A8437

uses a technique called Predictive Droop for regulat-

ing the output capacitor voltage after the completion

of a charging cycle. When the target output voltage

is reached, the converter stops charging and output

capacitor voltage droops due to leakage current. An

external resistor and capacitor connected from the

REG pin to ground will provide an RC discharge time

constant. This time constant can be selected to mirror

the droop rate of the output capacitor. When voltage at

the REG pin drops to 80% of the reference value, the

converter starts charging again and brings the output

capacitor back to target voltage again.

For example, if C = 10 μF, R = 10 MΩ and V0 / VT =

1.25, then T = 22 seconds. Assuming that the RC-dis-

charge characteristic of the output capacitor matches

that at the REG pin, we can predict that the output

voltage has drooped 20%, and therefore it is time to

recharge the output capacitor.

By implementing a Predictive Droop technique, no

additional leakage paths are introduced on the second-

ary side, which helps to keep power losses to a mini-

mum. By intentionally making the RC discharge time

constant of the REG pin shorter than that of the output

capacitor, we can regulate the output voltage to a win-

dow tighter than the default 20% hysteresis.

Voltage Regulation Using Direct Sensing If direct sens-

ing from the secondary side is desired, connect the

REG pin to a resistor divider network across the out-

put capacitor to enable output regulation. In this case,

the charging cut-off is still controlled by primary side

sensing (charging stops when reflected voltage reaches

31.5 V), but the regulation threshold is controlled by

the secondary side sensing. When the CHARGE pin

is high, and the sensed output voltage falls below the

lower VREG threshold, the flyback converter charges

the output capacitor again until the primary side sens-

ing stops further charging. This cycle repeats till the

CHARGE pin is pulled low.

The benefit of this method is that a lower output volt-

age can be selected independently, simply by chang-

ing the resistor divider ratio. For example, given

R1=10 MΩ, R2= 33.2 kΩ, and VREG(L)= 0.96 V, then:

VOUT(Low) = VREG(L) × ( R1/ R2 + 1) = 290 V . (2)

Selection of Switching Current Limit

The time required for an RC network to discharge

from V0 to VT is given by:

The A8437 features continuously adjustable peak

switching current between 0.4 and 1.2A. This is done

Allegro MicroSystems, Inc.

9

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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