S-24CM01C Ver la hoja de datos (PDF) - Unspecified

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S-24CM01C

2-WIRE SERIAL E2PROM

Unspecified 

2-WIRE SERIAL E2PROM

S-24CM01C

Rev.2.0_03_S

7. 3 Sequential read

When the S-24CM01C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following

a start condition both in current address read and random read, it responds with an acknowledge.

When an 8-bit data is output from the S-24CM01C synchronous to the SCL clock, the address counter is

automatically incremented.

When the master device responds with an acknowledge, the data at the next memory address is transmitted.

Response with an acknowledge by the master device has the memory address counter in the S-24CM01C

incremented and makes it possible to read data in succession. This is called “Sequential Read”.

The master device outputs stop condition not an acknowledge, the reading of S-24CM01C is ended.

Data can be read in succession in the sequential read mode. When the memory address counter reaches the last

word address, it rolls over to the first word address.

R

E

DEVICE A

ADDRESS D

SDA

LINE

1 D7

RA

/C

WK

A

C

K

D0 D7

A

C

K

D0 D7

NO ACK from

Master Device

S

A

T

C

O

K

P

D0 D7

D0

DATA (n)

DATA (n+1)

DATA (n+2)

DATA (n+x)

Figure 17 Sequential Read

18

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