A40MX02-PG100 Ver la hoja de datos (PDF) - Microsemi Corporation

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Fabricante

A40MX02-PG100

40MX and 42MX FPGA

Microsemi Corporation 

40MX and 42MX FPGA Families

2 40MX and 42MX FPGA Families

2.1

2.1.1

2.1.2

2.1.3

2.1.4

2.2

Features

The following sections list out various features of the 40MX and 42MX FPGA family devices.

High Capacity

• Single-Chip ASIC Alternative

• 3,000 to 54,000 System Gates

• Up to 2.5 kbits Configurable Dual-Port SRAM

• Fast Wide-Decode Circuitry

• Up to 202 User-Programmable I/O Pins

High Performance

• 5.6 ns Clock-to-Out

• 250 MHz Performance

• 5 ns Dual-Port SRAM Access

• 100 MHz FIFOs

• 7.5 ns 35-Bit Address Decode

HiRel Features

• Commercial, Industrial, Automotive, and Military Temperature Plastic Packages

• Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages

• QML Certification

• Ceramic Devices Available to DSCC SMD

Ease of Integration

• Mixed-Voltage Operation (5.0 V or 3.3 V for core and

I/Os), with PCI-Compliant I/Os

• Up to 100% Resource Utilization and 100% Pin Locking

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II

• Low Power Consumption

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

Product Profile

The following table gives the features of the products.

Table 1 • Product profile

Device

A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36

Capacity

System Gates

SRAM Bits

3,000

6,000

14,000

24,000

36,000

54,000

2,560

Logic Modules

Sequential

348

624

954

1,230

Combinatorial

295

547

336

608

912

1,184

Decode

24

24

Clock-to-Out

9.5 ns

9.5 ns

5.6 ns 6.1 ns 6.1 ns

6.3 ns

SRAM Modules

(64x4 or 32x8)

10

Dedicated Flip-Flops

348

624

954

1,230

DS2316 Datasheet Revision 16.0

3

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