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ICE5QSAG

Quasi-Resonant Controller

Infineon Technologies 

Quasi-Resonant Controller

Functional Description

(for high line). After the Q1 (see Figure 1) is turned off, every time when the falling voltage ramp of on ZCD pin

crosses the VZCD_CT threshold, a zero crossing is detected and ZC counter will increase by 1. It is reset every time

after the DRIVER output is changed to high.

To achieve the switch on at voltage valley, the voltage from the auxiliary winding is fed to a time delay network

(the RC network consists of RZC and CZC as shown in Figure 1) before it is applied to the zero-crossing detector

through the ZCD pin. The needed time delay to the main oscillation signal Δt should be approximately one

fourth of the oscillation period, TOSC (by transformer primary inductor and drain-source capacitor) minus the

propagation delay from the detected zero-crossing to the switch-on of the main switch tdelay, theoretically:

Δt

=

��������

4

−

������������

(2)

This time delay should be matched by adjusting the time constant of the RC network which is calculated as:

��td

=

������ .

������∙��������

������ +��������

(3)

3.3.2

Ringing suppression time

After Q1 (see Error! Reference source not found.) is turned off, there will be some oscillation on VDS, which will

also appear on the VZCD. To avoid mis-triggering by such oscillations to turn on the Q1, a ringing suppression

timer is implemented. This suppression time is depended on the voltage VZCD. If the voltage VZCD is lower than

the threshold VZCD_RS, a longer preset time tZCD_RS2 is applied. However, if the voltage VZCD is higher than the

threshold, a shorter time tZCD_RS1 is set.

3.3.2.1 Switch on determination

After the gate drive goes to low, it cannot be changed to high during ring suppression time.

After ring suppression time, the gate drive can be turned on when the ZC counter value is equal to up/down

counter value.

However, it is also possible that the oscillation between primary inductor and drain-source capacitor damps

very fast and IC cannot detect zero crossings event. In this case, a maximum off time is implemented. After gate

drive has been remained off for the period of TOffMax, the gate drive will be turned on again regardless of the ZC

counter values and VZCD. This function can effectively prevent the switching frequency from going lower than 20

kHz. Otherwise it will cause audible noise.

3.3.3

Switch off determination

In the converter system, the primary current is sensed by an external shunt resistor, which is connected

between source terminal of the internal MOSFET and the common ground. The sensed voltage across the shunt

resistor VCS is applied to an internal current measurement unit, and its output voltage V1 is compared with the

feedback voltage VFB. Once the voltage V1 exceeds the voltage VFB, the output flip-flop is reset. As a result, the

main power switch is switched off. The relationship between the V1 and the VCS is described by (see Figure 3):

��CS = ��D × ��CS

��1 = �������� ∙ ������ + ��������

(4)

where, VCS : CS pin voltage

ID

: power MOSFET current

RCS : resistance of the current sense resistor

V1

: voltage level compared to VFB

GPWM

Datasheet

: PWM-OP gain

9 of 27

V 2.1

2020-02-03

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