AT91RM9200(2003) Ver la hoja de datos (PDF) - Atmel Corporation

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AT91RM9200
(Rev.:2003)

ARM920T™- based Microcontroller

Atmel Corporation 

Ethernet MAC

Serial Peripheral

Interface

Two-wire Interface

USART

• Compatibility with IEEE Standard 802.3

• 10 and 100 Mbits per second data throughput capability

• Full- and half-duplex operation

• MII or RMII interface to the physical layer

• Register interface to address, status and control registers

• DMA interface, operating as a master on the Memory Controller

• Interrupt generation to signal receive and transmit completion

• 28-byte transmit and 28-byte receive FIFOs

• Automatic pad and CRC generation on transmitted frames

• Address checking logic to recognize four 48-bit addresses

• Supports promiscuous mode where all valid frames are copied to memory

• Supports physical layer management through MDIO interface control of alarm and update

time/calendar data in

• Supports communication with serial external devices

– Four chip selects with external decoder support allow communication with up to 15

peripherals

– Serial memories, such as DataFlash and 3-wire EEPROMs

– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and

Sensors

– External co-processors

• Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select

– Programmable phase and polarity per chip select

– Programmable transfer delays between consecutive transfers and between clock

and data per chip select

– Programmable delay between consecutive transfers

– Selectable mode fault detection

• Connection to PDC channel optimizes data transfers

– One channel for the receiver, one channel for the transmitter

– Next buffer support

• Compatibility with standard two-wire serial memory

• One, two or three bytes for slave address

• Sequential read/write operations

• Programmable Baud Rate Generator

• 5- to 9-bit full-duplex synchronous or asynchronous serial communications

– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous

Mode

– Parity generation and error detection

– Framing error detection, overrun error detection

– MSB- or LSB-first

– Optional break generation and detection

10 AT91RM9200

1768B–ATARM–08/03

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