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LTM4656Y

Synchronous Boost µModule Regulator with Input-Output Short Protection

Analog Devices 

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

IN-LINE PROTECTION SECTION

Referring to the Block Diagram, the input voltage is applied

to VIN. The power MOSFET MIN is controlled by a charge

pump high side drive that is slowly turned on after the

SHDN pin is either pulled up to VIN or driven from an open

collector drive rated to VIN. The UV pin has an internal 100k

resistor to VIN that can be used with an external resistor

to ground to set a UVLO trip point for VIN. This is valuable

to limit turn-on to a specific input voltage level. When

both the SHDN and UV pin thresholds are met, then the

gate voltage begins to ramp up at a control rate and the

MIN source pin will follow. Gate turn-on time is ~10ms.

The RSENSE in series with this path monitors the current

going to the boost converter. The LTM4656 monitors the

voltage drop between the SENSE1 and BVIN pins to protect

against overcurrent faults. An internal amplifier limits the

voltage across the internal 4mΩ current sense resistor

to 50mV. This is reduced to 25mV in a severe fault when

BVIN is below 2V. In this fault condition, a timer is started

inversely proportional to MOSFET stress. Before the timer

expires, the FLT pin pulls low to warn of an impending power

down. If the condition persists, the MOSFET is turned off,

and restarts after a cooldown period. BVIN needs at least

100µF capacitance to service proper current limit level to

eliminate any overtemperature timeout oscillations.

assure the MOSFET can handle this power dissipation for

that period of time. When TMR reaches 1.275V, the FLT

pin pulls low to indicate the detection of a fault condition.

If the condition persists, the pass transistor turns off when

TMR reaches the threshold of 1.375V. A 2µA current source

then continues to pull the TMR up. When TMR reaches

4.3V, the 2µA current reverses direction and starts to pull

the TMR pin low. When TMR reaches the retry threshold

of 0.5V, the GATE pin pulls high turning back on the pass

transistor. See overcurrent fault diagram in Figure 2.

–260

TMR = 1V

–220

–160

–120

–80

–40

0

0 10 20 30 40 50 60 70 80

VIN – SENSE1 (V)

4656 F01

Figure 1. Overcurrent TMR Current

vs VIN – SENSE1 Voltage

FAULT TIMER SECTION

VTMR(V)

A 0.01µF capacitor is connected internal to the TMR pin 1.375

and ground to set the times for early fault warning, fault 1.275

turn-off, and cooldown periods. This capacitor is selected

to assure the MIN MOSFET is turn-off fast enough. The

TMR charging current increases linearly from 8µA with VDS

VDS = 28V

ITMR = 120µA

CTMR = 0.01µF

VDS = 12V

ITMR = 35µA

CTMR = 0.01µF

< 0.5V to 120µA with VDS = 40V. VDS is inferred from the

drop across VIN and SENSE1. See Figure 1. The current 0.50

TIME

charging up this TMR pin during fault conditions depends

on the voltage difference across MIN MOSFET between

tFLT

= 90µs

tWARNING

= 8µs

the VIN and SENSE1 pins. This increase in TMR current is

to assure a faster turn off during an overcurrent fault with

tFLT = 221µs

TOTAL FAULT TIMER = tFLT + tWARNING

tWARNING

= 20µs

4656 F02

substantial voltage across the MIN MOSFET. This turn-off

time is correlated with the MIN MOSFET SOA capability to

Figure 2. Overcurrent Fault Time with 0.01µF

Rev. 0

10

For more information www.analog.com

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