M37735MHBXXXFP Ver la hoja de datos (PDF) - Renesas Electronics

Número de pieza

componentes Descripción

Fabricante

M37735MHBXXXFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Renesas Electronics 

PRELIMINARY NSootimcee: pTahriasmisentroict alimfinitsalasrpeescuifbicjeactitotno. change.

MITSUBISHI MICROCOMPUTERS

M37735MHBXXXFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

The bus interface unit operates using one of the waveforms (1) to

(10) shown in Figure 5. The standard waveforms are (1) and (2).

The ALE signal is used to latch only the address signal from the

multiplexed signal containing data and address.

The E signal becomes “L” when the bus interface unit reads an

instruction code or data from the memory or when it writes data to

the memory. Whether to perform read or write is controlled by the

R/W signal. The E (except for that in the single-chip mode) and R/W

signals are not directly output to the outside. In the memory expansion

mode or the microprocessor mode, read signal RDE and write signals

WEL, WEH are output, instead of E and R/W, to the outside of the

chip. During signal E is “L”, signal RDE becomes “L” (in the read cycle)

or signals WEL and WEH become “L” (in the write cycle).

Waveform (1) in Figure 5 is used to access a single byte or two bytes

simultaneously. To read or write two bytes simultaneously, the first

address accessed must be even. Furthermore, when accessing an

external memory area in the memory expansion mode or the

microprocessor mode, set the bus width selection input pin (BYTE)

to “L” (external data bus has a width of 16 bits). The data bus in the

internal memory area is always treated as the 16-bit bus independent

of BYTE.

Internal clock φ

Port P2

(1)

E

ALE

Port P2

(2)

E

ALE

AD

Access time

A D A+1 D

Access time

Port P2

(3)

E

ALE

A

D

Access time

Port P2

(4)

E

ALE

Port P2

(5)

E

ALE

A

D

A +1

D

Access time

A

D A+1 D

Access time

Port P2

(6)

E

ALE

A D A+1 D

Access time

Fig. 5 Bus access timing

Internal clock φ

Port P2

(7)

E

ALE

Port P2

(8)

E

ALE

Port P2

(9)

E

ALE

Port P2

(10)

E

ALE

A

D

Access time

A

D

A+1

D

Access time

A

D

A+1 D

Access time

A D A+1

D

Access time

A : Address

D : Data

During signal E is “L” in the memory expansion mode or

the microprocessor mode, signal RDE becomes “L”

(in the read cycle) or signals WEL and WEH become “L”

(in the write cycle).

10

Share Link: