CL7512AFC256-6 Ver la hoja de datos (PDF) - Clear Logic
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CL7512AFC256-6 Datasheet PDF : 14 Pages
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CL7512AE Laser Processed Logic Devices
AC Electrical Specifications
I/O Element Timing Parameters
Symbol
Parameter
Conditions
tPD1 Input to non-registered output
CL = 35 pF
tPD2 I/O input to non-registered output
CL = 35 pF
tSU
Global clock setup time
tH
Global clock hold time
tFSU Global clock setup time of fast input
tFH
Global clock hold time of fast input
tCO1 Global clock to output delay
CL = 35 pF
tCH
Global clock high time
tCL
Global clock low time
tASU Array clock setup time
tAH
Array clock hold time
tACO1 Array clock to output delay
CL = 35 pF
tACH Array clock high time
tACL
Array clock low time
tCNT Minimum global clock period
fCNT Maximum internal global clock frequency
tACNT Minimum array clock period
fACNT Maximum internal array clock frequency
Speed: -6
Min Max
6.0
6.0
3.7
0.0
2.5
0.5
1.0
3.3
3.0
3.0
0.8
1.9
1.0
6.2
3.0
3.0
6.4
156.3
6.4
156.3
Speed: -7
Min Max
7.5
Unit
ns
7.5
ns
4.9
ns
0.0
ns
3.0
ns
0.0
ns
1.0
4.5
ns
3.0
ns
3.0
ns
1.6
ns
2.1
ns
7.8
ns
3.0
ns
3.0
ns
8.4
ns
119.0
MHz
8.4
ns
119.0
MHz
7Ka tbl 06B1
Page 9
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