CL3256AQC208-7 Ver la hoja de datos (PDF) - Clear Logic
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CL3256AQC208-7 Datasheet PDF : 14 Pages
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CL3256A Laser Processed Logic Devices
AC Electrical Specifications
I/O Element Timing Parameters
Speed: -4
Symbol
Parameter
Conditions Min Max
tPD1 Input to non-registered output
CL = 35 pF
4.5
tPD2 I/O input to non-registered output
CL = 35 pF
4.5
tSU Global clock setup time
3.0
tH
Global clock hold time
0.0
tCO1 Global clock to output delay
CL = 35 pF
1.0 2.8
tCH Global clock high time
2.0
tCL Global clock low time
2.0
tASU Array clock setup time
1.4
tAH Array clock hold time
0.8
tACO1 Array clock to output delay
CL = 35 pF
4.4
tACH Array clock high time
2.0
tACL Array clock low time
2.0
tCNT Minimum global clock period
5.2
fCNT Max. internal global clock frequency
192.3
tACNT Minimum array clock period
5.2
fACNT Max. internal array clock frequency
192.3
Speed: -5
Min Max
5.0
5.0
3.2
0.0
1.0
3.0
2.0
2.0
1.0
0.8
5.2
2.0
2.0
5.5
181.8
5.5
181.8
Speed: -6
Min Max Unit
6.0 ns
6.0 ns
3.7
ns
0.0
ns
1.0
3.3
ns
3.0
ns
3.0
ns
0.8
ns
1.9
ns
1.0 6.2 ns
3.0
ns
3.0
ns
6.4 ns
156.3
MHz
6.4 ns
156.3
MHz
3KA tbl 06A1
Page 9
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