VG36256161A Ver la hoja de datos (PDF) - Vanguard International Semiconductor
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componentes Descripción
Fabricante
VG36256161A Datasheet PDF : 69 Pages
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VIS
Preliminary
VG36256401A
VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
A.C Characteristics : (Ta = 0 to 70°C V DD = 3.3V ±0.3V, VSS = 0V)
symbol
A.C. Parameter
tRC
tRCD
tRP
tRRD
tRAS
tCK2
tCK3
tCH
tCL
tAC2
tAC3
tT
tCCD
tOH
tLZ
tHZ2
tHZ3
tIS
tIH
tSRX
tPDE
tRSC
tDPL
tDAL2
tDAL3
tBDL
tREF
Row cycle time
RAS to CAS delay
Precharge to refresh/row activate command
Row activate to row activate delay
Row activate to precharge time
CL2
Clock cycle time
CL3
Clock high time
Clock low time
Access time from CLK
CL2
(positive edge)
CL3
Transition time of CLK (Rise and Fall)
CAS to CAS Delay time
Data output hold time
Data output low impedance
CL2
Data output high impedance
CL3
Data/Address/Control Input setup time
Data/Address/Control Input hold time
Minimum CKE ”High”for Self-Refresh exit
Power Down Exit set-up time
Mode Register Set Cycle
Data-in to precharge
Data-in to ACT (REF) Command
CL2
CL3
Last data in to burst stop
Refresh time (8,192 refresh cycles)
-75
Min.
Max.
60
-8H
Min.
Max.
unit
70
20
20
15
20
ns
15
20
37.5 100,000
50
100,000
7.5
10
7.5
10
2.25
3
2.25
3
ns
4
6
4
6
1
10
1
10
1
1
CLK
2
3
0
0
4
6
ns
4
6
1
2
0.5
1
1
1
CLK
2
2
ns
2
2
CLK
2
1
CLK
2clk+tRP
2clk+tRP
1
1clk+tRP
1clk+tRP
1
ns
CLK
64
64
ms
note
9
Document : 1G5-0155
Rev.1
Page 7
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