VG36256161A Ver la hoja de datos (PDF) - Vanguard International Semiconductor
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VG36256161A Datasheet PDF : 69 Pages
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VIS
Preliminary
VG36256401A
VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
(2/3)
Current state CS RAS CA WE Address
Command
Action
Notes
Read with auto H X X X X
precharge
L H H HX
DESL
NOP
Continue burst to end → Prcharging
Continue burst to end → Prcharging
L H H LX
BST
Illegal for single bank, but illegal for
multibanks interleave
L H L H BA, CA, A10 READ/READA Illegal for single bank, but illegal for
multibanks interleave
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA
ACT
ILLEGAL
3
L L H L BA, A10
PRE/PALL
ILLEGAL
3
L L L HX
PEF/SELF
ILLEGAL
L L L L Op - Code MRS
ILLEGAL
Write with auto H X X X X
precharge
L H H HX
L H H LX
DESL
NOP
BST
Continue burst to end → Write
recovering with auto precharge
Continue burst to end → Write
recovering with auto precharge
ILLEGAL
L H L H BA, CA, A10 READ/READA Illegal for single bank, but legal for
multibanks interleave
L H L L BA, CA, A10 WRIT/WRITA Illegal for single bank, but legal for
multibanks interleave
L L H H BA, RA
ACT
ILLEGAL
3
L L H L BA, A10
PRE/PALL
ILLEGAL
3
L L L HX
PEF/SELF
ILLEGAL
L L L L Op - Code MRS
ILLEGAL
precharging
H X X XX
L H H HX
L H H LX
DESL
NOP
BST
Nop → Enter idle after tRP
Nop →Enter idle after tRP
Nop →Enter idle after tRP
L H L H BA, CA, A10 READ/READA ILLEGAL
3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
3
L L H H BA, RA
ACT
ILLEGAL
3
L L H L BA, A10
PRE/PALL
Nop → Enter idle after tRP
L L L HX
PEF/SELF
ILLEGAL
L L L L Op - Code MRS
ILLEGAL
Row activating H X X X X
L H H HX
L H H LX
DESL
NOP
BST
Nop → Enter row active idle after tRCD
Nop →Enter row active idle after tRCD
Nop →Enter row active idle after tRCD
L H L H BA, CA, A10 READ/READA ILLEGAL
3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
3
L L H H BA, RA
ACT
ILLEGAL
3,9
L L H L BA, A10
PRE/PALL
ILLEGAL
3
L L L HX
PEF/SELF
ILLEGAL
L L L L Op - Code MRS
ILLEGAL
Document : 1G5-0155
Rev.1
Page 11
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