VV5430 Ver la hoja de datos (PDF) - STMicroelectronics
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VV5430 Datasheet PDF : 33 Pages
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Serial Communication
VV5430
8. Serial Communication
The VV5430 includes a full duplex (two-wire) serial interface, and can be controlled and configured by a host processor. The base
bus address for the VV5430 is 20H, but the two least significant bits of the address (SAB0, SAB1) can be selected by hard-wiring
pins 20 and 16. This allows up to four separate camera devices to be controlled on one serial link, which, for example, makes
multiplexing of camera outputs possible.
The serial interface reads or writes data to a set of Registers that define the characterisation of the sensor, and control certain
operations.
8.1 Serial Communication Protocol
The host must perform the role of a communications master and the camera acts as either a slave receiver or transmitters
communication between host and camera takes the form of three or five byte messages of 8-bit data, with a maximum serial clock
(SCL) frequency of 100kHz. Since the serial clock is generated by the host, the host determines the data transfer rate.
The host processor initiates a message by forcing both Serial Data (SDA) and Serial Clock (SCL) low. The first byte addresses
the required device, and defines either a READ message (four bytes to follow) or a WRITE message (two bytes to follow). After
the camera has acknowledged a valid address (ACK, bit 9 of SCL), the host then either reads four bytes of data from the camera
or transmits a further two bytes to the camera. The data transfer protocol on the bus is illustrated below:
Start condition
Read/Write bit Acknowledge from receiver
SDA
SCL
S
MSB
12
7 8 9 1 2 3-8 9
P
ACK
ACK
Stop condition
Figure 8 : Data Transfer Protocol
CD5430F-A
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