CY7C1020CV33-10ZXC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1020CV33-10ZXC Datasheet PDF : 9 Pages
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CY7C1020CV33
AC Test Loads and Waveforms[4]
3.3V
OUTPUT
30 pF
R 317Ω
3.0V
R2 GND
351Ω
ALL INPUT PULSES
90%
10%
(a)
Rise Time: 1 V/ns
(b)
90%
10%
High-Z characteristics:
R 317 Ω
3.3V
OUTPUT
5 pF
Fall Time: 1 V/ns
(c)
R2
351Ω
Switching Characteristics Over the Operating Range[4]
-10
-12
-15
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU[7]
tPD[7]
tDBE
tLZBE
tHZBE
Write Cycle[8]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[5]
OE HIGH to High-Z[5, 6]
CE LOW to Low-Z[5]
CE HIGH to High-Z[5, 6]
CE LOW to Power-up
CE HIGH to Power-down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
10
12
15
ns
10
12
15
ns
3
3
3
ns
10
12
15
ns
5
6
7
ns
0
0
0
ns
5
6
7
ns
3
3
3
ns
5
6
7
ns
0
0
0
ns
10
12
15
ns
5
6
7
ns
0
0
0
ns
5
6
7
ns
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tAW
Address Set-up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Set-up to Write End
5
6
8
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low-Z[5]
WE LOW to High-Z[5, 6]
0
0
0
ns
3
3
3
ns
5
6
7
ns
tBW
Byte Enable to End of Write
7
8
9
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. This parameter is guaranteed by design and is not tested.
8. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and
the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05133 Rev. *E
Page 4 of 9
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