TSL2580FN(2010) Ver la hoja de datos (PDF) - austriamicrosystems AG
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TSL2580FN Datasheet PDF : 35 Pages
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
1
7
11
8
1
S Slave Address Wr A Command Code A
8
1
Byte Count = N A
8
Data Byte 1
TAOS098 − MARCH 2010
1
A ...
8
Data Byte 2
1
A ...
8
Data Byte N
11
AP
Figure 13. SMBus Block Write or I2C Write Protocols
NOTE: The I2C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a
Stop condition. See the Command Register on page 12 for additional information regarding the Block Read/Write protocol.
lid 1
7
11
S Slave Address Wr A
8
Command Code
11
7
11
A Sr Slave Address Rd A
8
Byte Count = N
1
A ...
8
1
va Data Byte 1
A
8
Data Byte 2
1
A ...
8
Data Byte N
11
AP
1
ill Figure 14. SMBus Block Read or I2C Read (Combined Format) Protocols
NOTE: The I2C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiates
a Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
G t Register Set
s The TSL258x is controlled and monitored by sixteen registers and a command register accessed through the
A t serial interface. These registers provide for a variety of control functions and can be read to determine results
of the ADC conversions. The register set is summarized in Table 2.
s n Table 2. Register Address
m te ADDRESS
RESISTER NAME
REGISTER FUNCTION
R/W
−−
COMMAND
Specifies register address
W
a n 00h
CONTROL
Control of basic functions
01h
TIMING
Integration time/gain control
o 02h
INTERRUPT
Interrupt control
c 03h
THLLOW
Low byte of low interrupt threshold
R/W
04h
THLHIGH
High byte of low interrupt threshold
l 05h
THLLOW
Low byte of high interrupt threshold
06h
THLHIGH
High byte of high interrupt threshold
a 07h
ANALOG
Analog control register
ic 12h
ID
Part number / Rev ID
13h
CONSTANT
Number 4 (for SMBus block reads)
14h
DATA0LOW
ADC channel 0 LOW data register
n 15h
DATA0HIGH
ADC channel 0 HIGH data register
R
16h
DATA1LOW
ADC channel 1 LOW data register
h 17h
DATA1HIGH
ADC channel 1 HIGH data register
c18h
TIMERLOW
Manual integration timer LOW register
19h
TIMERHIGH
Manual integration timer HIGH register
eThe mechanics of accessing a specific register depends on the specific SMB protocol used. See the section
Ton SMBus protocols, above. In general, the COMMAND register is written first to specify the specific
control/status register for following read/write operations.
The LUMENOLOGY r Company
r
Copyright E 2010, TAOS Inc.
r
www.taosinc.com
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