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ST18D952

DIGITAL SIGNAL PROCESSOR (DSP) CHIP

STMicroelectronics 

ST18952

6 Bus Switch Unit

The three memory spaces can be extended off-chip through the bus switch unit (BSU)

peripheral. The figure below shows the layout of the D950Core BSU.

Figure 6.1 D950Core Bus Switch Unit

D 950 Co re

INTERNAL MEMORIES

& PERIPHERALS

XD

16

X

MEM.

Y

MEM.

P

MEM.

IRD/XRD/YRD

16

INTERNAL MEMORIES

& PERIPHERALS

16

16

IWR/XWR/YWR

INTERNAL MEMORIES

& PERIPHERALS

IID/I XD/IYD

DEID/DEXD/DEYD

16

XA

BUS

YD

SWITCH

YA

UNIT

ID

IB S/XBS/YBS

16

IA

DTACK

BSU_CLK

ED

EA

EXRD/DS

EXWR/RD

EYRD/DS

EYWR/RD

EIRD/DS

EIWR/RD

DTACKin

I DT_EN

RESET

AS-DSP

2

2

2

16

16

VR02020A

6.1 BSU operation

The BSU recognizes a bus cycle when a bus extension strobe (IBSE, XBSE or YBSE) goes

active. The BSU decodes the address value to determine if an external memory access is

requested on the I, X or Y-bus and generates the appropriate signals on the external bus side.

The BSU generates software wait-states, depending on the setting of the control register.

If more than one external memory access is attempted at one instruction cycle, they are

serviced sequentially in the following order: I-bus, X-bus, Y-bus.

Each external access requires one basic instruction clock cycle (2 CLKIN cycles), extended

by, at least, one wait-state (2 CLKIN cycles). The number of wait-states can be extended,

either by software with the BSU control registers (see Section 6.2), or by hardware with the

DTACK input signal.

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