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RMWL38001

37-40 GHz Low Noise Amplifier MMIC

Fairchild Semiconductor 

Electrical Characteristics (At 25°C), 50 Ω system, Vd = +4V, Quiescent Current Idq = 50 mA

Parameter

Frequency Range

Gate Supply Voltage (Vg)1

Noise Figure

Gain Small Signal at Pin = -20 dBm

GainVariation vs Frequency

Gain at 1 dBm Compression

Power Output at 1 dB Compression

Power Output Saturated

Drain Current at Pin = -20 dBm

Drain Current at 1dB Compression

Input Return Loss (Pin = -15 dBm)

Output Return Loss (Pin = -15 dBm)

OIP3

Min

Typ

Max

37

40

-0.5

2.7

4.0

22

1.5

21

13.5

15

50

55

12

13

23

Note:

1: Typical range of negative gate voltage is -0.9 to -0.1 V to set typical Idq of 50 mA.

Units

GHz

V

dB

dB

dB

dB

dBm

dBm

mA

mA

dB

dB

dBm

Application Information

CAUTION: THIS IS AN ESD SENSITIVE DEVICE.

Chip carrier material should be selected to have GaAs compatible thermal coefficient of expansion and high thermal

conductivity such as copper molybdenum or copper tungsten. The chip carrier should be machined, finished flat, plated with

gold over nickel and should be capable of withstanding 325°C for 15 minutes.

Die attachment should utilize Gold/Tin (80/20) eutectic alloy solder and should avoid hydrogen environment for PHEMT

devices. Note that the backside of the chip is gold plated and is used as RF and DC ground.

These GaAs devices should be handled with care and stored in dry nitrogen environment to prevent contamination of

bonding surfaces. These are ESD sensitive devices and should be handled with appropriate precaution including the use of

wrist grounding straps. All die attach and wire/ribbon bond equipment must be well grounded to prevent static discharges

through the device.

Recommended wire bonding uses 3 mils wide and 0.5 mil thick gold ribbon with lengths as short as practical allowing for

appropriate stress relief. The RF input and output bonds should be typically 0.012" long corresponding to a typical 2 mil gap

between the chip and the substrate material.

RF IN

DRAIN DRAIN DRAIN DRAIN

SUPPLY SUPPLY SUPPLY SUPPLY

Vd1

Vd2

Vd3

Vd4

MMIC CHIP

RF OUT

GROUND GATE SUPPLY

(Back of the Chip)

Vg1

GATE SUPPLY

Vg1

Figure 1. Functional Block Diagram

©2004 Fairchild Semiconductor Corporation

RMWL38001 Rev. C

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