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Quad net
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Logic Cells (Internal)
Clock Pad
7DEOH (FOLSVH3OXV &ORFN 'HOD\
3DUDPHWHUV
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*OREDO
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Clock signal generated internally 1.51 ns (max)
Clock signal generated externally 2.06 ns (max)
1.73 ns (max)
&ORFN 6HJPHQW
tPGCKa
tBGCK
7DEOH (FOLSVH3OXV *OREDO &ORFN 'HOD\
3DUDPHWHU
0LQ
Global clock pin delay to quad net
-
Global clock tree delay (quad net to
flip-flop)
-
9DOXH
0D[
1.34 ns
0.56 ns
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/RFNHG /RRS
Programmable Clock
External Clock
Global Clock Buffer
Global Clock
tPGCK
Clock
Select
tBGCK
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