IDT70V657S Ver la hoja de datos (PDF) - Unspecified

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IDT70V657S

HIGH-SPEED 3.3V 32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

Unspecified 

IDT70V657S

High-Speed 3.3V 32K x 36 Asynchronous Dual-Port Static RAM

Waveform of Read Cycles(5)

tRC

ADDR

CE(6)

tAA (4)

tACE (4)

tAOE (4)

OE

BEn

tABE (4)

Preliminary

Industrial and Commercial Temperature Ranges

R/W

DATAOUT

tLZ (1)

tOH

(4)

VALID DATA

BUSYOUT

tHZ (2)

tBDD (3,4)

5615 drw 06

NOTES:

1. Timing depends on which signal is asserted last, OE, CE or BEn.

2. Timing depends on which signal is de-asserted first CE, OE or BEn.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

ICC

50%

ISB

tPD

50%

.

5615 drw 07

11

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