ICS9112M-17-T Ver la hoja de datos (PDF) - Integrated Circuit Systems

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ICS9112M-17-T

Low Skew Output Buffer

Integrated Circuit Systems 

ICS9112-17

Output to Output Skew

The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the

inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase

difference will maintained from REF to all outputs.

If applications requiring zero output-output skew, all the outputs must equally loaded.

If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded than

CLKOUT, CLKA/B will lag the CLKOUT.

Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them to

have different rise times and different times crossing the measurement thresholds.

REF input and

all outputs

loaded Equally

REF input and CLKA/B

outputs loaded equally, with

CLKOUT loaded More.

REF input and CLKA/B

outputs loaded equally, with

CLKOUT loaded Less.

Timing diagrams with different loading configurations

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