AV9120M-08 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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AV9120M-08 Datasheet PDF : 7 Pages
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ICS9120-08
ICS9120-09
Pin Configuration
8-Pin SOIC
8-Pin SOIC
Functionality
X1, X2
(MHz)
-
14.318
-
(-09 only)
PD#
0
1
33.9
(MHz)
Low
33.868
16.9
(MHz)
Low
16.934
24.6
(MHz)
Low
24.576
14.3
(MHz)
Low
14.318
Note: (Pin 8) is internally pulled-up to VDD and, therefore, may
be left disconnected or driven by open collector logic.
Pin Descriptions for ICS9120-08
PIN NUMBER
1
2
3
4
5
6
7
8
PIN NAME
X1
VDD
GND
CLK3
CLK1
CLK2
REF
X2
TYPE
Input
Power
Power
Output
Output
Output
Output
Output
DESCRIPTION
Crystal or external clock source. Has feedback bias for crystal.
Power supply input.
Ground return for Pin 2.
16.934 MHz target output clock for stereo codec.
24.576 MHz target output clock for stereo codec.
33.868 MHz target output clock for OPL4.
14.318 MHz reference clock buffered output.
Crystal output drive.
Pin Descriptions for ICS9120-09
PIN NUMBER
1
2
3
4
5
6
7
8
PIN NAME
X1
VDD
GND
CLK3
CLK1
CLK2
REF
PD#
TYPE
Input
Power
Power
Output
Output
Output
Output
Input
DESCRIPTION
External clock source.
Power supply input.
Ground return for Pin 2.
16.934 MHz target output clock for stereo codec.
24.576 MHz target output clock for stereo codec.
33.868 MHz target output clock for OPL4.
14.318 MHz reference clock buffered output.
Power-down input powers down entire device when low; has pull-up.
2
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