AS7C33256PFD16A-200TQC Ver la hoja de datos (PDF) - Alliance Semiconductor

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AS7C33256PFD16A-200TQC

3.3V 256K × 16/18 pipeline burst synchronous SRAM

Alliance Semiconductor 

March 2002

AS7C33256PFD16A

AS7C33256PFD18A

®

3.3V 256K × 16/18 pipeline burst synchronous SRAM

Features

• Organization: 262,144 words × 16 or 18 bits

• Fast clock speeds to 200 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns

• Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns

• Fully synchronous register-to-register operation

• “Flow-through” mode

• Dual-cycle deselect

- Single-cycle deselect also available (AS7C33256PFS16A/

AS7C33256PFS18A)

• Pentium®1 compatible architecture and timing

• Asynchronous output enable control

• Economical 100-pin TQFP package

• Byte write enables

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate VDDQ

• 30 mW typical standby power in power down mode

• NTD™<Superscript>1 pipeline architecture avail-

able

• (AS7C33256NTD16A/AS7C33256NTD18A)

1. Pentium® is a registered trademark of Intel Corporation. NTD™ is a

trademark of Alliance Semiconductor Corporation. All trademarks men-

tioned in this document are the property of their respective owners.

Logic block diagram

Pin arrangement

CLK

ADV

ADSC

ADSP

A[17:0]

GWE

BWb

BWE

BWa

CE0

CE1

CE2

ZZ

OE

18

Power

down

LBO

CLK

CS Burst logic

CLR

D

Q 18

CS Aredgdisrteesrs

CLK

256K × 16/18

16 18

Memory

array

16/18 16/18

D DQb Q

Bryetge iWsterriste

CLK

D DQa Q

Bryetge iWsterriste

CLK

D EnableQ

register

CE

CLK

D EnableQ

redgeilsatyer

CLK

2

OE

Output

registers

CLK

Input

registers

CLK

16/18

FT DQ [a,b]

NC 1

NC 2

NC 3

VDDQ 4

VSSQ 5

NC 6

NC 7

DQb 8

DQb 9

VSSQ 10

VDDQ 11

DQb 12

DQb 13

FT 14

VDD 15

NC 16

VSS 17

DQb 18

DQb 19

VDDQ 20

VSSQ 21

DQb 22

DQb 23

DQpb/NC 24

NC 25

VSSQ 26

VDDQ 27

NC 28

NC 29

NC 30

TQFP 14 × 20mm

80 A17

79 NC

78 NC

77 VDDQ

76 VSSQ

75 NC

74 DQpa/NC

73 DQa

72 DQa

71 VSSQ

70 VDDQ

69 DQa

68 DQa

67 VSS

66 NC

65 VDD

64 ZZ

63 DQa

62 DQa

61 VDDQ

60 VSSQ

59 DQa

58 DQa

57 NC

56 NC

55 VSSQ

54 VDDQ

53 NC

52 NC

51 NC

Note: pins 24, 74 are NC for ×16.

Selection guide

Minimum cycle time

Maximum pipelined clock frequency

Maximum pipelined clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

–200

5

200

3

570

160

30

–183

5.4

183

3.1

540

140

30

–166

6

166

3.5

475

130

30

–133

7.5

133

4

425

100

30

–100

10

100

5

325

90

30

Units

ns

MHz

ns

mA

mA

mA

3/8/02; v.1.6

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