AS7C33256PFD16A-200TQC Ver la hoja de datos (PDF) - Alliance Semiconductor

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Fabricante

AS7C33256PFD16A-200TQC

3.3V 256K × 16/18 pipeline burst synchronous SRAM

Alliance Semiconductor 

AS7C33256PFD16A

AS7C33256PFD18A

®

AC test conditions

• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

+3.0V

90%

Z0 = 50Ω

90%

DOUT

10%

10%

GND

50Ω

VL = 1.5V

for 3.3V I/O;

30 pF* = VDDQ/2

for 2.5V I/O

DOUT

353Ω / 1538Ω

Thevenin equivalent:

+3.3V for 3.3V I/O;

/+2.5V for 2.5V I/O

319Ω / 1667Ω

5 pF*

GND *including scope

and jig capacitance

Figure A: Input waveform

Figure B: Output load (A)

Figure C: Output load (B)

Notes

1 For test conditions, see AC Test Conditions, Figures A, B, C.

2 This parameter measured with output load condition in Figure C.

3 This parameter is sampled, but not 100% tested.

4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.

5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.

6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other syn-

. chronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled.

7 Write refers to GWE, BWE, BW[a:b].

8 Chip select refers to CE0, CE1, CE2.

Package Dimensions

100-pin quad flat pack (TQFP)

TQFP

Min Max

A1 0.05 0.15

A2 1.35 1.45

b 0.22 0.38

c 0.09 0.20

D 13.90 14.10

E 19.90 20.10

e 0.65 nominal

Hd 15.90 16.10

He 21.90 22.10

L 0.45 0.75

L1 1.00 nominal

α

0°

7°

Dimensions in millimeters

c

L1

L

Hd

D

b

e

He E

A1 A2

α

3/8/02; v.1.6

Alliance Semiconductor

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