AS7C33256PFD18A(2002) Ver la hoja de datos (PDF) - Alliance Semiconductor

Número de pieza

componentes Descripción

Fabricante

AS7C33256PFD18A
(Rev.:2002)

3.3V 256K × 16/18 pipeline burst synchronous SRAM

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AS7C33256PFD16A

AS7C33256PFD18A

®

Timing characteristics over operating range

Parameter

Symb –200

–183

–166

–133

–100

Notes

ol Min Max Min Max Min Max Min Max Min Max Unit 1

Clock frequency

fMax

–

200

–

183

–

-

166

–

133

–

100 MHz

Cycle time (pipelined mode)

tCYC 5 – 5.4 – 6 – 7.5 – 10 – ns

Cycle time (flow-through mode)

tCYCF 9 – 10 – 10 – 12 – 12 – ns

Clock access time (pipelined mode)

tCD – 3.0 – 3.1 – 3.5 – 4.0 – 5.0 ns

Clock access time (flow-through mode) tCDF – 8.5 – 9 – 9 – 10 – 12 ns

Output enable LOW to data valid

tOE – 3.0 – 3.1 – 3.5 – 4.0 – 5.0 ns

Clock HIGH to output Low Z

tLZC 0 – 0 – 0 – 0 – 0 – ns 2,3,4

Data output invalid from clock HIGH tOH 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – ns 2

Output enable LOW to output Low Z tLZOE 0 – 0 – 0 – 0 – 0 – ns 2,3,4

Output enable HIGH to output High Z tHZOE – 3.0 – 3.1 – 3.5 – 4.0 – 4.5 ns 2,3,4

Clock HIGH to output High Z

tHZC – 3.0 – 3.1 – 3.5 – 4.0 – 5.0 ns 2,3,4

Output enable HIGH to invalid output tOHOE 0 – 0 – 0 – 0 – 0 – ns

Clock HIGH pulse width

tCH 2.2 – 2.4 – 2.4 – 2.5 – 3.5 – ns 5

Clock LOW pulse width

tCL 2.2 – 2.4 – 2.4 – 2.5 – 3.5 – ns 5

Address setup to clock HIGH

tAS 1.4 – 1.4 – 1.5 – 1.5 – 2.0 – ns 6

Data setup to clock HIGH

tDS 1.4 – 1.4 – 1.5 – 1.5 – 2.0 – ns 6

Write setup to clock HIGH

tWS 1.4 – 1.4 – 1.5 – 1.5 – 2.0 – ns 6,7

Chip select setup to clock HIGH

tCSS 1.4 – 1.4 – 1.5 – 1.5 – 2.0 – ns 6,8

Address hold from clock HIGH

tAH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6

Data hold from clock HIGH

tDH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6

Write hold from clock HIGH

tWH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6,7

Chip select hold from clock HIGH

tCSH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6,8

ADV setup to clock HIGH

tADVS 1.4 – 1.4 – 1.5 – 1.5 – 2.0 – ns 6

ADSP setup to clock HIGH

tADSPS 1.4 – 1.4 – 1.5 – 1.5 – 2.0 – ns 6

ADSC setup to clock HIGH

tADSCS 1.4 – 1.4 – 1.5 – 1.5 – 2.0 – ns 6

ADV hold from clock HIGH

tADVH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6

ADSP hold from clock HIGH

tADSPH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6

ADSC hold from clock HIGH

tADSCH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6

1 "Notes," on page 10

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3/8/02; v.1.6

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