NCP1615(2013) Ver la hoja de datos (PDF) - ON Semiconductor
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NCP1615 Datasheet PDF : 44 Pages
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NCP1615
Table 1. PIN FUNCTION DESCRIPTION
Pin Number
NCP1615C/D NCP1615A/B
Name
1
N/A
FBHV
2
1
FB
3
2
Restart
4
3
FOVP/BUV
5
4
Control
6
5
FFcontrol
7
6
Fault
8
7
STDBY
9
N/A
PSTimer
10
8
PFCOK
Function
High voltage PFC feedback input. An external resistor divider is used to sense the
PFC bulk voltage. The divider high side resistor chain from the PFC bulk voltage
connects to this pin. An internal high−voltage switch disconnects the high side
resistor chain from the low side resistor when the PFC is latched or in PSM in
order to reduce input power.
This pin receives a portion of the PFC output voltage for the regulation and the
dynamic response enhancer (DRE) that speeds up the loop response when the
output voltage drops below 95.5% of the regulation level. VFB is also the input
signal for the Soft−Overvoltage Comparators as well as the Undervoltage (UVP)
Comparator. The UVP Comparator prevents operation as long as VFB is lower
than 12% of the reference voltage (VREF). The Soft−Overvoltage Comparator
(Soft−OVP) gradually reduces the duty ratio to zero when VFB exceeds 105% of
VREF. A 250 nA sink current is built−in to trigger the UVP protection and disable
the part if the feedback pin is accidentally open. A dedicated comparator monitors
the bulk voltage and disables the controller if a line overvoltage fault is detected.
This pin receives a portion of the PFC output voltage for determining the restart
level after entering standby mode.
Input terminal for the Fast Overvoltage (Fast−OVP) and Bulk Undervoltage (BUV)
Comparators. The circuit disables the driver if the VFOVP/BUV exceeds the VFOVP
threshold which is set 2% higher than the reference for the Soft−OVP comparator
monitoring the FB pin. This allows the both pins to receive the same portion of the
output voltage. The BUV Comparator trips when VFOVP/BUV falls below 76% of the
reference voltage. A BUV fault disables the driver and grounds the PFCOK pin.
The BUV function has no action whenever the PFCOK pin is in low state. Once
the downstream converter is enabled the BUV Comparator monitors the output
voltage to ensure it is high enough for proper operation of the downstream con-
verter. A 250 nA current pulls down the pin and disable the controller if the pin is
accidentally open.
The error amplifier output is available on this pin. The network connected between
this pin and ground sets the regulation loop bandwidth. It is typically set below 20
Hz to achieve high power factor ratios. This pin is grounded when the controller is
disabled. The voltage on this pin gradually increases during power up to achieve a
soft−start.
This pin sources a current representative to the line current. Connect a resistor
between this pin and GND to generate a voltage representative of the line current.
When this voltage exceeds the internal 2.5 V reference, the circuit operates in
critical conduction mode. If the pin voltage is below 2.5 V, a dead−time is gen-
erated that approximately equates [83 ms • (1 − (VFFcontrol/VREF))]. By this means,
the circuit increases the deadtime when the current is smaller and decreases the
deadtime as the current increases.
The circuit skips cycles whenever VFFcontrol is below 0.65 V to prevent the PFC
stage from operating near the line zero crossing where the power transfer is par-
ticularly inefficient. This does result in a slightly increased distortion of the current.
If superior power factor is required, offset the voltage on this pin by more than
0.75 V to inhibit skip operation.
The controller enters fault mode if the voltage of this pin is pulled above or below
the fault thresholds. A precise pull up current source allows direct interface with an
NTC thermistor. Fault detection triggers a latch or auto−recovery depending on
device version.
This pin is used to force the controller into standby mode.
Power saving mode (PSM) timer adjust. A capacitor between this pin and GND,
CPSTimer, sets the delay time before the controller enters power saving mode.
Once the controller enters power saving mode the IC is disabled and the current
consumption is reduced to a maximum of 100 mA. The input filter capacitor dis-
charge function is available while in power saving mode. The device enters PSM if
the voltage on this pin exceeds the PSM threshold, VPS_in. A secondary side con-
troller optocoupler pulls down on the pin to prevent the controller from entering
PSM when the load is connected to the power supply. The controller is enabled
once VPSTimer drops below VPS_out.
This pin is grounded until the PFC output has reached its nominal level. It is also
grounded if the controller detects a fault. The voltage on this pin is 5 V once the
controller reaches regulation.
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