LZ93N61 Ver la hoja de datos (PDF) - Sharp Electronics
Número de pieza
componentes Descripción
Fabricante
LZ93N61 Datasheet PDF : 12 Pages
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SERIAL DATA FORMAT
D I (pin 9)
D2 (pin 10)
Do (pin 8)
Do
DI D2 D3 D. D, De
D7
n
NOTE :
D&D7 are latched by the rising edge of pulse D, (pin 9).
By the falling edge of pulse Do (pin 8), the shutter speed is decided.
LZ93N61
DESCRIPTION OF EXTERNAL SYNCHRONOUS SHUT-
TER MODE
1. When EXMD = H, this mode is given priority over other
modes. On applying falling edge of trigger input to
EXST (pin 11), the IC reads at the rising edge of HDI
and latches the V period counter value, and controls
final output of the OFDX pulse during this H period.
(The pulse must lasts until HDI goes high.)
2. Once latched, the value of V period counter is re-
tained until the next trigger is input as long as EXMD
= H, even trigger input is for odd (ODD) w even (EVEN)
field, the storage time of another field becomes the
same as the field with trigger input automatically.
Note that when changing in high speed shutter di-
rection, the internally stored data is used first, This
caue-es the delay to control by one field.
[Trigger input disabled range]
To match ODD storage time with EVEN stomge time, the
pulse start position is set at 20/283 H for NTSC and
22/335 H for PAL. This means that inputting the trigger
at 18/280, 281 H in NTSC mode and 20/332, 333 H in
PAL mode is made disabled.
NTSC 17/279 H
PAL 19/331 H
18/280 H
20/W2 H
19/281 H
21/W H
20/282 H
22/=4 H
21/2S3 H
23/=5 H
22/2W H
241W H
HOI
n
n
I-1
n
EXST
~~~~ ~
(PATTERN)
a
b (INVALID) C (EVEN IWALIO)
d[
e
OFDX 000/lst, 3rd FIELD ~
WEN/2nd, 4th FIELD ~
,
[
(PATTERN)
a
END
w
b-u
c
d
e
000 START EVEN START
295
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