MC33364D2G Ver la hoja de datos (PDF) - ON Semiconductor
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MC33364D2G Datasheet PDF : 16 Pages
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MC33364
The MOC8102 has a typical current transfer ratio (CTR)
of 100% with 25% tolerance. When the TL431 is full−on,
5 mA will be drawn from the transistor within the
MOC8102. The transistor should be in saturated state at that
time, so its collector resistor must be
Rcollector
+
Vref * Vsat
ILED
+
5.0
V * 0.3
5.0 mA
V
+
940
W
Since a resistor of 5.0 k is internally connected from the
reference voltage to the feedback pin of the MC33364, the
external resistor can have a higher value
Rext
+
R3
+
(Rint)(Rcollector)
(Rint) * (Rcollector)
+
(5.0 k)(940)
5.0 k * 940
+ 1157 W [ 1200 W
This completes the design of the voltage feedback circuit.
In no load condition there is only a current flowing
through the optoisolator diode and the voltage sense divider
on the secondary side.
The load at that condition is given by:
Rnoload
+
Vout
(ILED ) Idiv)
+
(5.0
6.0
mA )
V
0.25
mA)
+
1143
W
The output filter pole at no load is:
fph
+
(
2p
1
Rnoload
Cout
)
+
1
(2p)(1143)(300
mF)
+
0.46
Hz
In heavy load condition the ILED and Idiv is negligible. The
heavy load resistance is given by:
Rheavy
+
Vout
Iout
+
6.0
2.0
V
A
+
3.0
W
The output filter pole at heavy load of this output is
fph
+
(2p
1
RheavyCout)
+
1
(2p)(3)(300
mF)
+
177
Hz
The gain exhibited by the open loop power supply at the
high input voltage will be:
2
ǒǒ Ǔ Ǔ A +
Vin max * Vout Ns
(Vin max)(Verror)(Np)
+
(382
(382
V * 6.0 V)2(7)
V)(1.2 V)(139)
The maximum
approximately:
+ 15.53 + 23.82 dB
recommended bandwidth is
fc
+
fs
min
5
+
70
kHz
5
+
14
kHz
The gain needed by the error amplifier to achieve this
bandwidth is calculated at the rated load because that yields
the bandwidth condition, which is:
ǒ Ǔ ǒ Ǔ Gc + 20 log
fc
fph
*A+
20 log
14 kHz
177
* 23.82 dB
+ 14.14 dB
The gain in absolute terms is:
Ac + 10(Gcń20) + 10(14.14ń20) + 5.1
Now the compensation circuit elements can be calculated.
The output resistance of the voltage sense divider is given by
the parallel combination of resistors in the divider:
Rin + Rupper || Rlower + 10 k || 14 k + 5833 W
R9 + (Ac) (Rin) + 29.75 k [ 30 k
ƪ ƫ C8 +
1
+ 382 pF [ 390 pF
2p (Ac) (Rin) (fc)
The compensation zero must be placed at or below the
light load filter pole:
ƪ ƫ C7 +
1
+ 11.63 mF [ 10 mF
2p (R9) (fpn)
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