MRF141 Ver la hoja de datos (PDF) - Tyco Electronics
Número de pieza
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Fabricante
MRF141 Datasheet PDF : 10 Pages
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Table 2. Common Source S–Parameters (VDS = 28 V, ID = 5 A) continued
f
MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 360
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 400
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S11
|S11|
φ
0.967
174
0.967
174
0.969
173
0.970
173
0.970
173
0.970
172
0.972
172
0.971
172
0.971
171
0.971
171
0.970
171
0.969
170
0.964
170
0.959
170
0.958
170
S21
|S21|
φ
0.21
26
0.20
26
0.20
23
0.19
29
0.17
25
0.17
27
0.16
28
0.15
27
0.13
29
0.15
29
0.15
32
0.15
29
0.16
32
0.15
29
0.15
21
S12
|S12|
φ
0.060
91
0.084
89
0.081
82
0.072
80
0.069
80
0.072
71
0.078
68
0.084
70
0.086
74
0.087
79
0.081
72
0.079
65
0.081
57
0.081
54
0.086
58
S22
|S22|
φ
0.978
169
1.030
167
0.994
170
0.963
170
0.951
172
0.985
167
0.970
165
0.953
165
0.949
168
0.962
167
0.976
164
0.969
164
0.972
165
0.976
165
0.953
167
RF POWER MOSFET CONSIDERATIONS
MOSFET CAPACITANCES
The physical structure of a MOSFET results in capacitors
between the terminals. The metal anode gate structure de-
termines the capacitors from gate–to–drain (Cgd), and gate–
to–source (Cgs). The PN junction formed during the
fabrication of the MOSFET results in a junction capacitance
from drain–to–source (Cds).
These capacitances are characterized as input (Ciss), out-
put (Coss) and reverse transfer (Crss) capacitances on data
sheets. The relationships between the inter–terminal capaci-
tances and those given on data sheets are shown below. The
Ciss can be specified in two ways:
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate. In the latter case the numbers are lower.
However, neither method represents the actual operat-
ing conditions in RF applications.
Cgd
GATE
Cgs
DRAIN
Cds
SOURCE
Ciss = Cgd = Cgs
Coss = Cgd = Cds
Crss = Cgd
LINEARITY AND GAIN CHARACTERISTICS
In addition to the typical IMD and power gain data pres-
ented, Figure 4 may give the designer additional information
on the capabilities of this device. The graph represents the
small signal unity current gain frequency at a given drain cur-
rent level. This is equivalent to fT for bipolar transistors.
REV 9
8
Since this test is performed at a fast sweep speed, heating of
the device does not occur. Thus, in normal use, the higher
temperatures may degrade these characteristics to some ex-
tent.
DRAIN CHARACTERISTICS
One figure of merit for a FET is its static resistance in the
full–on condition. This on–resistance, VDS(on), occurs in the
linear region of the output characteristic and is specified un-
der specific test conditions for gate–source voltage and drain
current. For MOSFETs, VDS(on) has a positive temperature
coefficient and constitutes an important design consideration
at high temperatures, because it contributes to the power
dissipation within the device.
GATE CHARACTERISTICS
The gate of the MOSFET is a polysilicon material, and is
electrically isolated from the source by a layer of oxide. The
input resistance is very high — on the order of 109 ohms —
resulting in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage
slightly in excess of the gate–to–source threshold voltage,
VGS(th).
Gate Voltage Rating — Never exceed the gate voltage
rating. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gate Termination — The gate of this device is essentially
capacitor. Circuits that leave the gate open–circuited or float-
ing should be avoided. These conditions can result in turn–
on of the device due to voltage build–up on the input
capacitor due to leakage currents or pickup.
Gate Protection — This device does not have an internal
monolithic zener diode from gate–to–source. If gate protec-
tion is required, an external zener diode is recommended.
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