MC141519T Ver la hoja de datos (PDF) - Motorola => Freescale

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componentes Descripción

Fabricante

MC141519T

LCD Segment Driver

Motorola => Freescale 

PIN DESCRIPTIONS

VDD AND VSS

P02

Power is supplied to the driver using these two pins. VDD is

A bus clock input that is used for data bus timing synchroniza-

power and VSS is ground.

tion. This pin is connected to P02 of MC68HC05L11.

V<1>, V<3>, V<4>

These are the levels of voltage generated from an external

voltages divider (Fig. 2). These voltage provide different voltage

levels for shaping up the display output waveforms Seg0 -

Seg159.

DOFF

This is an output from MC68HC05L11 to signal the back-

plane driver to turn off LCD. If this pin is clear, the segment

driver supplies LCD with driving signal. If this pin is set, the seg-

ment driver outputs is high-impedance and LCD display is dis-

abled.

FRM

A periodic active high input to the segment driver for frame

timing synchronization. This pin is connected to the signal FRM

of MC68HC05L11. The frequency depends on the bias ratio

and BPCLK signal.

BPCLK

A periodic clock output from MC68HC05L11 to the seg-

ment driver for timing synchronization. The signal controls the

refresh timing of LCD display.

M

A periodic output from backplane driver. This pin is used for

synchronization among display drivers.

D0 - D6

A seven-bit input-only data bus which is connected to the

D0 - D6 of MC68HC05L11. These pins are used for address

input and control input. Refer to Fig.1 for definition.

TST

The test pin should be pulled-low or connected to D7 of

MC68HC05L11 during normal operation.

BS

This is an active low input for chip select.

RAA

It is a strobe signal from MC68HC05L11 indicating that a valid

segment control data is on D0 - D6 for a period of P02.

CR1, CR2

These two control signals from MC68HC05L11 to Segment

driver describing the nature of the content in D0 - D6. The effect of

CRs are shown on Fig 1.

SD1, SD2

These two pins are two bi-directional data lines connecting to

the UD2 or LD2 and UD1 or LD1 respectively. These allow the dis-

play data from MC68HC05L11 entering the segment driver in both

directions.

SHCLK

This is the shift clock from MC68HC05L11 to segment driver for

clocking the serial data on SD1 and SD2. See Timing Diagram for

illustration.

DDIR

It is an input pin carrying the signal from MC68HC05L11 to seg-

ment driver to control the direction of the serial data. In lower panel

mode, if DDIR is set, the serial data enters the segment driver

through SD1 and leaves the segment driver through SD2. If DDIR is

clear, SD1 and SD2 are redefined as an output and input respec-

tively.

SEG0 - SEG159

These 160 output lines provide the segment driving signal to

the LCD panel. They are all in high-impedance state while the dis-

play is turned off (i.e. DOFF is set).

MC141519

3–100

MOTOROLA

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