VNI8200XP-32 Ver la hoja de datos (PDF) - STMicroelectronics

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VNI8200XP-32

Octal high-side smart power solid-state relay with serial/parallel selectable interface on-chip

STMicroelectronics 

VNI8200XP-32

List of figures

List of figures

Figure 1: Block diagram ..............................................................................................................................7

Figure 2: Pin connection (top view) ............................................................................................................8

Figure 3: Reverse polarity protection........................................................................................................17

Figure 4: Maximum demagnetization energy vs. load current, typical values ..........................................18

Figure 5: SPI mode diagram .....................................................................................................................21

Figure 6: Output channel enable/disable behavior ...................................................................................22

Figure 7: Power Good diagnostic .............................................................................................................23

Figure 8: Watchdog reset .........................................................................................................................24

Figure 9: LED driving array .......................................................................................................................27

Figure 10: Typical circuit for switching regulation VDC-out = 3.3 V .............................................................29

Figure 11: Typical circuit for switching regulation VDC-out = 5 V ................................................................30

Figure 12: SPI directional logic convention...............................................................................................31

Figure 13: PowerSSO-36 thermal impedance vs. time ............................................................................32

Figure 14: Thermal behavior.....................................................................................................................33

Figure 15: Serial timing .............................................................................................................................34

Figure 16: dV/dt(ON) and dV/dt(OFF) time diagram test conditions ........................................................35

Figure 17: td(ON) and td(OFF) time diagram test conditions...........................................................................35

Figure 18: PowerSSO-36 package outline ...............................................................................................36

Figure 19: PowerSSO-36 package outline details ....................................................................................37

Figure 20: PowerSSO-36 package outline details (section B-B) ..............................................................37

Figure 21: PowerSSO-36 tube shipment outline ......................................................................................39

Figure 22: PowerSSO-36 tape dimension outline ....................................................................................40

Figure 23: PowerSSO-36 reel shipment outline .......................................................................................41

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