W89C840F Ver la hoja de datos (PDF) - Winbond

Número de pieza

componentes Descripción

Fabricante

W89C840F

100/10Mbps Ethernet Controller

Winbond 

MTXCLK

I

MTXD[3:0]

O

MTXEN

O

MMDC

O

MMDIO

I/O

MCRS

I

MCOL

I

MRXDV

I

MRXER

I

W89C840F

Transmit clock:

MTXCLK is a continuous uniformed clock source

driven by the external PHY. It provides the timing

reference for the signals MTXEN and MTXD.

MTXCLK should be either 25MHz or 2.5MHz clock.

Transmit Data:

This nibble byte width transmit data bus is synchronized

with MTXCLK. It should be latched by the external

PHY at the rising edge of MTXCLK. MTXD[0] is the

least significant bit.

Transmit enable:

It indicates that transmits activity to an external PHY. It

will be synchronized with MTXCLK.

MII management reference clock.

It is the reference clock of MMDIO. Each data bit will

be latched at the MMDC rising edge.

MII management data input/output.

This pin is used to transfer the MII control and status

information between PHY and MAC.

Carrier Sense Signal:

This shall be asserted by PHY device when media is

busy, and deasserted when media is idle. MCRS shall

keep asserted, even at the duration of a collision.

Collision detected:

This shall be asserted by the PHY device upon detecting

a collision happened over the medium. It will be asserted

and lasted until collision condition wholly vanishes.

Received data valid:

This pin is driven by PHY device. It will be asserted

when received data is coming and present, and

deasserted at the end of the frame. MRXDV is

synchronized with MRXCLK from PHY device.

Received data error:

This pin is driven by PHY device. It indicates a data

conversion error is detected by PHY device. The

assertion of MRXER should be lasted for longer than a

period of MRXCLK. When MRXER asserted,

W89C840F will report a Receive Error detection and a

CRC error.

Publication Release Date:April 1997

-9-

Revision A1

Share Link: