W89C840F Ver la hoja de datos (PDF) - Winbond

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componentes Descripción

Fabricante

W89C840F

100/10Mbps Ethernet Controller

Winbond 

W89C840F

MRXCLK

I

MRXD[3:0]

I

Received clock source:

This clock is from PHY device. It will be either 25Mhz

or 2.5Mhz receive clock, determined by auto-negotiation

device in PHY and supported by W89C840F. The

minimun duty cycle at its high state or low state of

MRXCLK should be 35% of the nominal period under

all condition. PHY device should drive MRXCLK as a

continuous clock.

Received data pins:

This is driven by external 100/10 Mbps PHY. MRXD

should be syncronized with clock source MRXCLK and

valid only when MRXDV is valid. MRXD[0] is the least

significant bit.

Functional Description

Receive direct memory access function

On receiving a data packet, the receive DMA function will transfer these data from the internal receive

FIFO which has a size of 4k bytes to the host memory with the assistance of the on-chip PCI bus master.

During the transaction cycle, the media access controller(MAC) requests the receive DMA state machine to

move the data in the receive FIFO onto the PCI bus, and then move it to the host memory with a kind of data

structure which is constructed and described by descriptors.

A number of receive descriptors in the chip, which generated by chip itself, are used to specify the

descriptor structure and indicate the memory spaces for storing the received packet data. The receive

descriptors also are used to store the received packet status when a valid packet is received. Each

descriptor has a size of 4 long words that resides in the host memory. The first 32 bits are used to keep the

received packet status information. The second 32 bits are used to specify the descriptor structure type and

the size of the received data buffer. The remains 64 bits are used to specify the size and the address of the

allocated memory for this data buffer and the next one.

The received packet can be described by a single descriptor or multiple descriptors. It depends on the

configuration, previously set by software driver, and the received packet length. The received packet data also

can be stored in a single data buffer or multiple data buffers.

The descriptor structure can be either a ring structure or a chain structure. A mixed structure mode

is also allowed.

In the descriptors with the ring structure, Host allocates a big continuous memory for keeping all the

descriptor information. Each descriptor can point to two data buffers addresses to store the received packet

data. Though the data buffers are not necessarily be contiguous, the descriptors must be contiguous one after

the other.

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