LTC1235CN-TRPBF Ver la hoja de datos (PDF) - Linear Technology

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LTC1235CN-TRPBF

Microprocessor Supervisory Circuit

Linear Technology 

LTC1235

PIN FUNCTIONS

high when ever there is a transition on the WDI pin, or

LOW LINE goes low. The watchdog timer can be disabled

by floating WDI (see Figure 11).

RESET (Pin 15): Logic output for μP reset control. The

LTC1235 provides three ways to generate μP reset. First,

whenever VCC falls below either the reset voltage threshold

(4.65V, typically) or VBATT, RESET goes active low. After

VCC returns to 5V, the reset pulse generator forces RESET

to remain active low for a minimum of 140ms. Second,

when the watchdog timer is enabled but not serviced

prior to the time-out period, the reset pulse generator

also forces RESET to active low for a minimum of 140ms

for every time-out period (see Figure 11). Third, when the

PB RST pin stays active low for a minimum of 40ms,

RESET is forced low by reset pulse generator. The RESET

signal will remain active low for a minimum of 140ms from

the moment the push-button reset input is released from

logic low level.

RESET (Pin 16): RESET is an active high logic output. It

is the inverse of RESET.

BLOCK DIAGRAM

VBATT

VCC

BACKUP

CE IN

PFI

PB RST

WDI

M2

M1

MEMORY

LOGIC

CHARGE

PUMP

–

C2

+

+

C1

–

1.3V

GND

VCC

OSC

60k

LEVEL SENSE

AND

DEBOUNCE

TRANSITION

DETECTOR

–

+

RESET PULSE

GENERATOR

WATCHDOG

TIMER

VOUT

BATT ON

LOW LINE

CE OUT

PFO

RESET

RESET

WDO

1235 BD

1235fa

7

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