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LTC1235
(Rev.:Rev0)

Microprocessor Supervisory Circuit

Linear Technology 

LTC1235

APPLICATI S I FOR ATIO

Voltage Output

During normal operation, the LTC1235 uses a charge

pumped NMOS power switch to achieve low dropout and

low supply current. This power switch can deliver up to

50mA to VOUT from VCC and has a typical on resistance of

5Ω. The VOUT pin should be bypassed with a capacitor of

0.1µF or greater to ensure stability. Use of a larger bypass

capacitor is advantageous for supplying current to heavy

transient loads.

When operating currents larger than 50mA are required

from VOUT, or a lower dropout (VCC - VOUT voltage differ-

ential) is desired, the LTC1235 provides BATT ON output

to drive the base of external PNP transistor (Figure 3).

Another alternative to provide higher current is to connect

a high current Schottky diode from the VCC pin to the VOUT

pin to supply the extra current.

ANY PNP POWER TRANSISTOR

+5V

0.1µF

+3V

R1

BATT ON

VCC

VOUT

LTC1235

VBATT

GND

0.1µF

LTC1235 F03

Figure 3. Using BATT ON to Drive External PNP Transistor

The LTC1235 is protected for safe area operation with

short circuit limit. Output current is limited to approxi-

mately 200mA. If the device is overloaded for a long period

of time, thermal shutdown turns the power switch off until

the device cools down. The threshold temperature for

thermal shutdown is approximately 155°C with about

10°C of hysteresis which prevents the device from oscil-

lating in and out of shutdown.

The PNP switch was not chosen for the internal power

switch because it injects unwanted current into the sub-

strate. This current is collected by the VBATT pin in com-

petitive devices and adds to the charging current of the

battery which can damage lithium batteries. LTC1235

uses a charge pumped NMOS power switch to eliminate

unwanted charging current while achieving low dropout

and low supply current. Since no current goes to the

substrate, the current collected by VBATT pin is strictly

junction leakage.

Conditional Battery Backup

LTC1235 provides an unique feature to either allow VOUT

to be switched to VBATT or to disable the CMOS RAM

battery backup function when primary power is lost.

Disabling the battery backup function is useful in conserv-

ing the backup battery's life when the SRAM doesn't need

battery backup during long term storage of a computer

system, or delivery of the computer system to the end

user.

The BACKUP pin (Pin 8) is used to serve this feature on

power-down. When VCC is falling through the reset voltage

threshold, the status of the BACKUP pin (logic low or logic

high) is stored in the Memory Logic (see BLOCK DIA-

GRAM). If the stored status is logic high and VCC fall to

50mV greater than VBATT, a 125Ω PMOS switch, M2,

connects the VBATT input to VOUT and the battery switchover

comparator, C2, shuts off the NMOS power switch, M1.

M2 is designed for very low dropout voltage (input-to-

output differential). This feature is advantageous for low

current applications such as battery backup in CMOS RAM

and other low power CMOS circuitry. If the stored status

is logic low and VCC falls to 50mV greater than VBATT, the

Memory Logic keeps M2 off and C2 shuts off M1. VOUT is

in Battery Saving Mode (see Figure 4). The supply current

in both mode is 1µA maximum.

On power-ups, C2 keeps M1 off before VCC reaches 70mV

higher than VBATT. On the first power-up after the battery

is replaced (with power off), the status stored in the

Memory Logic is undetermined. VOUT could be either in

Battery Backup Mode or in Battery Saving Mode. When

VCC is 70mV greater than VBATT, M1 connects VOUT to VCC.

C2 has typically 20mV of hysteresis to prevent spurious

switching when VCC remains nearly equal to VBATT and the

status stored in the Memory Logic is high. The response

time of C2 is approximately 20µs.

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