LTC1235CN(Rev0) Ver la hoja de datos (PDF) - Linear Technology

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LTC1235CN
(Rev.:Rev0)

Microprocessor Supervisory Circuit

Linear Technology 

LTC1235

PI FU CTIO S

WDI: Watchdog Input, WDI, is a three level input. Driving

WDI either high or low for longer than the watchdog time-

out period, forces both RESET and WDO low. Floating WDI

disables the Watchdog Timer. The timer resets itself with

each transition of the Watchdog Input (see Figure 11).

WDO: Watchdog logic output. When the watchdog input

remains either high or low for longer than the watchdog

time-out period, WDO goes low. WDO is set high whenever

there is a transition on the WDI pin, or LOW LINE goes low.

The watchdog timer can be disabled by floating WDI (see

Figure 11).

CE IN: Logic input to the Chip Enable gating circuit. CE IN

can be derived from microprocessor's address line and/or

decoder output. See Applications Information Section and

Figure 6 for additional information.

CE OUT: Logic output from the Chip Enable gating circuit.

When VCC is above the reset voltage threshold, CE OUT is

a buffered replica of CE IN. When VCC is below the reset

voltage threshold CE OUT is forced high (see Figure 6).

BLOCK DIAGRA

VBATT

VCC

BACKUP

CE IN

PFI

PB RST

WDI

M2

M1

MEMORY

LOGIC

CHARGE

PUMP

–

C2

+

+

C1

–

1.3V

GND

OSC

LEVEL SENSE

AND

DEBOUNCE

TRANSITION

DETECTOR

–

+

RESET PULSE

GENERATOR

WATCHDOG

TIMER

VOUT

BATT ON

LOW LINE

CE OUT

PFO

RESET

RESET

WDO

LTC1235 BD

7

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