LTC2753UK-12 Ver la hoja de datos (PDF) - Linear Technology
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LTC2753UK-12 Datasheet PDF : 24 Pages
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LTC2753
TIMING CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
VDD = 2.7V to 3.3V
t22
t23
t24
CLR Timing
t25
READ Falling Edge to UPD Rising Edge
I/O Bus Hi-Z to Read Rising Edge
Read Falling Edge to I/O Bus Active
CLR Pulse Width Low
CONDITIONS
(Note 10)
(Note 10)
(Note 10)
MIN TYP MAX UNITS
● 10
ns
●
0
ns
● 35
ns
● 20
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specified pins is constant for
all output ranges if the IOUT1X and IOUT2X pins are held at ground.
Note 4: R1 is measured from RIN to RCOM; R2 is measured from REFA to
RCOM.
Note 5: Using LT1469 with CFEEDBACK = 15pF. A ±0.0015% settling time
of 1.7μs can be achieved by optimizing the time constant on an individual
basis. See Application Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.
Note 6: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1469; CFB = 27pF.
Note 7. Full-scale transition; REF = 0V.
Note 8. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1469.
Note 9. Calculation from Vn = √4⎯ ⎯k⎯T⎯R⎯B, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =
bandwidth (Hz).
Note 10. Guaranteed by design. Not production tested.
2753f
6
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