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74LVCH16374ADGG

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Nexperia B.V. All rights reserved 

Nexperia

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Symbol Parameter

Conditions

tdis

tW

tsu

th

fmax

tsk(o)

CPD

disable time

pulse width

set-up time

hold time

maximum

frequency

output skew

time

power

dissipation

capacitance

nOE to nQn; see Fig. 7

VCC = 1.2 V

VCC = 1.65 V to 1.95 V

VCC = 2.3 V to 2.7 V

VCC = 2.7 V

VCC = 3.0 V to 3.6 V

nCP HIGH; see Fig. 6

VCC = 1.65 V to 1.95 V

VCC = 2.3 V to 2.7 V

VCC = 2.7 V

VCC = 3.0 V to 3.6 V

nDn to nCP; see Fig. 8

VCC = 1.65 V to 1.95 V

VCC = 2.3 V to 2.7 V

VCC = 2.7 V

VCC = 3.0 V to 3.6 V

nDn to nCP; see Fig. 8

VCC = 1.65 V to 1.95 V

VCC = 2.3 V to 2.7 V

VCC = 2.7 V

VCC = 3.0 V to 3.6 V

see Fig. 6

VCC = 1.65 V to 1.95 V

VCC = 2.3 V to 2.7 V

VCC = 2.7 V

VCC = 3.0 V to 3.6 V

VCC = 3.0 V to 3.6 V

per input; VI = GND to VCC

VCC = 1.65 V to 1.95 V

VCC = 2.3 V to 2.7 V

VCC = 3.0 V to 3.6 V

-40 °C to +85 °C

Min Typ[1] Max

[2]

-

12

-

2.8 4.6 9.1

1.0 2.5 4.9

1.5 3.4 5.1

1.5 3.1 4.9

-40 °C to +125 °C Unit

Min

Max

-

- ns

2.8

10.5 ns

1.0

5.7 ns

1.5

6.5 ns

1.5

6.5 ns

5.0

-

-

5.0

4.0

-

-

4.0

3.0

-

-

3.0

3.0 1.5

-

3.0

- ns

- ns

- ns

- ns

4.0

-

-

4.0

3.0

-

-

3.0

1.9

-

-

1.9

1.9 0.3

-

1.9

- ns

- ns

- ns

- ns

3.0

-

-

3.0

2.5

-

-

2.5

1.1

-

-

1.1

+1.5 -0.3

-

1.5

- ns

- ns

- ns

- ns

100

-

-

80

125

-

-

100

150

-

-

120

150 300

-

120

[3] -

-

1.0

-

[4]

-

14.1

-

-

-

16.4

-

-

-

18.5

-

-

- ns

- ns

- MHz

- MHz

1.5 ns

- pF

- pF

- pF

[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2] tpd is the same as tPLH and tPHL; ten is the same as tPZL and tPZH; tdis is the same as tPLZ and tPHZ.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC2 x fi x N + Σ(CL x VCC2 x fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL x VCC2 x fo) = sum of the outputs

74LVC_LVCH16374A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 12 — 20 November 2018

© Nexperia B.V. 2018. All rights reserved

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