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CY14B108N-ZSP25XCT Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción
Fabricante
CY14B108N-ZSP25XCT
Cypress
Cypress Semiconductor Cypress
CY14B108N-ZSP25XCT Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CY14B108L, CY14B108N
8 Mbit (1024K x 8/512K x 16) nvSRAM
Features
20 ns, 25 ns, and 45 ns Access Times
Internally Organized as 1024K x 8 (CY14B108L) or 512K x 16
(CY14B108N)
Hands off Automatic STORE on Power Down with only a Small
Capacitor
STORE to QuantumTrap Nonvolatile Elements Initiated by
Software, Device Pin, or AutoStore on Power Down
RECALL to SRAM Initiated by Software or Power Up
Infinite Read, Write, and RECALL Cycles
200,000 STORE Cycles to QuantumTrap
20 year Data Retention
Single 3V +20%, -10% Operation
Commercial and Industrial Temperatures
48-Ball FBGA and 44/54-Pin TSOP-II Packages
Pb-free and RoHS Compliant
Functional Description
The Cypress CY14B108L/CY14B108N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 1024 Kbytes of 8 bits each or 512K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Logic Block Diagram[1, 2, 3]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A17
A18
A19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Quatrum Trap
VCC
VCAP
2048 X 2048 X 2
R
POWER
O
STORE
CONTROL
W
RECALL
D
E
STATIC RAM
STORE/RECALL
CONTROL
HSB
C
ARRAY
O
2048 X 2048 X 2
D
E
R
SOFTWARE
DETECT
A14 - A2
I
N
P
U
T
B
COLUMN I/O
U
F
F
E
R
COLUMN DEC
S
A9 A10 A11 A12 A13 A14 A15 A16
OE
WE
CE
BLE
BHE
Notes
1. Address A0 - A19 for x8 configuration and Address A0 - A18 for x16 configuration.
2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-45523 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 30, 2009
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