AD7522LD Ver la hoja de datos (PDF) - Analog Devices
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AD7522LD Datasheet PDF : 6 Pages
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~'..-
-
DIGITAL INPUT
1111111111
1000000001
1000000000
0111111111
0000000001
0000000000
ANALOG OUTPUT
-VREF (1 - 2010)
-VREF (1/2 + 2-10)
-VREF/2
-VREF (1/2 - 2010)
-VREF (2010)
0
Voo
+15V
Vcc
+5V TO +15V
AD7522
DIA
CONVERTER
Table I. Unipolar Code Table
BIPOLAR OPERATION
Figure 4:shows the analog circuit connections required for
26~
211 .SPC
20'_~
bipolar operation. The input code/ouput voltage relationship
is shown in Table II.
~
STROBE
OBI SOLETE VREF
t10V
Voo
Vcc
+1"5V +5VTnO +15V
CR2
27
R2
5 RfBI soon
6 ,'oun
AD7522
DAC
7 .'Dun
2' LDTR
R3
2Ok!1
R5
2Ok!1
Figure 4. Bipolar Operation
LOAD(1)/
HOLD(01
Figure 5. Single Byte Parallel Loading
When data is stable on the parallel inputs (DBO-DB9), it can be
transferred into the input buffer on the positive edge of the
strobe pulse.
Data is transferred from the input buffer to the DAC register
when LDAC is a Logic "1." LDAC is a level-actuated (versus
edge-triggered) function and must be held "high" at least
O.5l1sfor data transfer to occur.
TWO BYTE PARALLEL LOADING
Figures 6 and 7 show the logic connections and timing require-
ments for interfacing the AD75 22 to an 8-bit data bus for two
byte loading of a lO-bit word.
Voo
+15V
Vee
+5V TO +15V
With the DAC register loaded to 10 0000 0000 adjust
Rl so that ANALOG OUTPUT = OVo Alternatively,
Rl, R2 may be omitted and the ratios of R3, R4
varied for ANALOG OUTPUT = OV. Full-scale trimming
can be accomplished by adjusting the amplitude of
VREF or by varying the value of R5.
If Rl, R2 are not used, then resistors R3, R4 and R5
should be ratio matched to 0.05% to ensure gain error
performance to the data sheet specification. When
operating over a wide temperature range, it is important
that the resistors be of the same type so that their temper-
ature coefficients match.
DIGITAL INPUT
1111111111
1000000001
1000000000
0111111111
0000000001
0000000000
ANALOG OUTPUT
+VREF (1 - 2-9)
+VREF (Z-9)
0
-VREF (2-9)
-VREF (1 - 2-9)
-VREF
DO
e§
I
D7
D6
'" D5
"'
.I.-
D4
.c. D
I-
iii
D2
.. DI
DO
MSB
10
DB8
11
DB7 12
DB6 13
DB5 14
DB4 15
DB3 16
DB2 17
DBI 18
D80
LSB
19
AD7522
DIA
CONVERTER
26
21 SPC
20 . seD
LBS
HBS
LDAC
Figure 60 Two Byte Parallel Loading
DATA
BUS LEAST SIGNIfICANT
DATA BYTE
MOST SIGNIFICANT
DATA BYTE
LOAD LEAST SIGNifiCANT
LBS
BYTE INTO INPUT REGISTER
Table 1/. Bipolar Code Table
HBS
LOAO MOST SIGNifiCANT..
BYTE INTO INPUT REGISTER
SINGLE BYTE PARALLEL LOADING
Figure 5 illustrates the logic connections for loading single byte
parallel data into the input buffer. DBO should be grounded on
"K" and "T" versions, and DBO and DBI should be grounded
on ")" and "S" versions for monotonic operation of the DAC.
DB9 is always the MSB, whether 8-bit, 9-bit, or lO-bit linear
AD7522's are used.
LDAC
UPDATDEAC---rI
OUTPU=T:::J L
Figure 7. Timing Diagram
First, the least significant data byte (DBO through DB7) is
loaded into the input buffer on the positive edge of LBS. Sub-
sequently, the data bus is used for status indication and
-5-
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