ADN2817ACP Ver la hoja de datos (PDF) - Analog Devices
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ADN2817ACP Datasheet PDF : 35 Pages
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Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADN2817/ADN2818
AUT OM OD E 1
VCC 2
VREF 3
NIN 4
PIN 5
SL ICEP 6
SL I CEN 7
VEE 8
AD N 2817
24 VCC
23 VEE
22 L OS
21 SDA
20 SCK
19 SAD D R5
18 VCC
17 VEE
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1
AUTOMODE
2
VCC
3
VREF
4
NIN
5
PIN
6
SLICEP
7
SLICEN
8
VEE
9
THRADJ
10
REFCLKP
11
REFCLKN
12
VCC
13
VEE
14
CF2
15
CF1
16
LOL
17
VEE
18
VCC
19
SADDR5
20
SCK
21
SDA
22
LOS
23
VEE
24
VCC
25
CLKOUTN
26
CLKOUTP
27
SQUELCH
28
DATAOUTN
29
DATAOUTP
30
VEE
31
VCC
32
VBER
Exposed Pad Pad
Type1
DI
P
AO
AI
AI
AI
AI
P
AI
DI
DI
P
P
AO
AO
DO
P
P
DI
DI
DI
DO
P
P
DO
DO
DI
DO
DO
P
P
AO
P
Figure 4. Pin Configuration
Description
Set to Logic Low to enable analog voltage output mode for BER monitor
Power for Limamp, LOS.
Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
GND for Limamp, LOS.
LOS Threshold Setting Resistor.
Differential REFCLK Input. 12.3 MHz to 200 MHz.
Differential REFCLK Input. 12.3 MHz to 200 MHz.
VCO Power.
VCO GND.
Frequency Loop Capacitor.
Frequency Loop Capacitor.
Loss of Lock Indicator. LVTTL active high.
FLL Detector GND.
FLL Detector Power.
Slave Address Bit 5.
I2C Clock Input.
I2C Data Input.
Loss of Signal Detect Output. Active high. LVTTL.
Output Buffer, I2C GND.
Output Buffer, I2C Power.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Disable Clock and Data Outputs. Active high. LVTLL.
Differential Recovered Data Output. CML.
Differential Recovered Data Output. CML.
Phase Detector, Phase Shifter GND.
Phase Detector, Phase Shifter Power.
Relative BER monitor output. Referred to GND, Analog Voltage Output.
Connect to GND
1Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Rev.Pr A | Page 9 of 35
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