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ADN2807ACP

155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

At medium jitter frequencies, the gain and tuning range of the

VCO are not large enough to track the input jitter. In this case,

the VCO control voltage becomes large and saturates, and the

VCO frequency dwells at one or the other extreme of its tuning

range. The size of the VCO tuning range, therefore, has only a

small affect on the jitter accommodation. The delay-locked loop

control voltage is now larger; therefore, the phase shifter takes

on the burden of tracking the input jitter. The phase shifter

range, in UI, can be seen as a broad plateau on the jitter

tolerance curve. The phase shifter has a minimum range of 2 UI

at all data rates.

The gain of the loop integrator is small for high jitter

frequencies, so larger phase differences are needed to make the

loop control voltage big enough to tune the range of the phase

shifter. Large phase errors at high jitter frequencies cannot be

tolerated. In this region, the gain of the integrator determines

the jitter accommodation. Since the gain of the loop integrator

declines linearly with frequency, jitter accommodation is lower

with higher jitter frequency. At the highest frequencies, the loop

gain is very small, and little tuning of the phase shifter can be

expected. In this case, jitter accommodation is determined by

ADN2807

the eye opening of the input data, the static phase error, and the

residual loop jitter generation. The jitter accommodation is

roughly 0.5 UI in this region. The corner frequency between the

declining slope and the flat region is the closed loop bandwidth

of the delay-locked loop, which is roughly 5 MHz for OC-12

data rates and 600 kHz for OC-3 data rates.

JITTER PEAKING

IN ORDINARY PLL

JITTER

GAIN

(dB)

ADN2807

Z(s)

X(s)

o

n psh

d psh

c

f (kHz)

Figure 14. Jitter Response vs. Conventional PLL

Rev. A | Page 11 of 20

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