AD9954YSVZ-REEL7 Ver la hoja de datos (PDF) - Analog Devices
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AD9954YSVZ-REEL7 Datasheet PDF : 40 Pages
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AD9954
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
I/O UPDATE 1
DVDD 2
DGND 3
AVDD 4
AGND 5
AVDD 6
AGND 7
OSC/REFCLK 8
OSC/REFCLK 9
CRYSTAL OUT 10
CLKMODESELECT 11
LOOP_FILTER 12
PIN 1
AD9954
TOP VIEW
(Not to Scale)
36 RESET
35 PWRDWNCTL
34 DVDD
33 DGND
32 AGND
31 COMP_IN
30 COMP_IN
29 AVDD
28 COMP_OUT
27 AVDD
26 AGND
25 AVDD
13 14 15 16 17 18 19 20 21 22 23 24
Figure 4. Pin Configuration
Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to
analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V. The DVDD pins (Pin 2 and Pin 34) must be
powered to 1.8 V.
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
I/O
1
I/O UPDATE
I
2, 34
DVDD
I
3, 33, 42 DGND
I
4, 6, 13, 16, AVDD
I
18, 19, 25,
27, 29
5, 7, 14, 15, AGND
I
17, 22, 26,
32
8
OSC/REFCLK
I
9
OSC/REFCLK
I
10
CRYSTAL OUT
O
11
CLKMODESELECT I
12
LOOP_FILTER
I
20
IOUT
O
21
IOUT
O
23
DACBP
I
24
DAC_RSET
I
28
COMP_OUT
O
30
COMP_IN
I
Description
The rising edge transfers the contents of the internal buffer memory to the I/O registers.
See Synchronization—Register Updates (I/O UPDATE) section for details.
Digital Power Supply Pins (1.8 V).
Digital Power Ground Pins.
Analog Power Supply Pins (1.8 V).
Analog Power Ground Pins.
Oscillator Input/Complementary Reference Clock. When the REFCLK port is operated in
single-ended mode, REFCLK should be decoupled to AVDD with a 0.1 μF capacitor.
Oscillator Input/Reference Clock. See Table 5 for details on the OSC/REFCLK operation.
Output of the Oscillator Section.
Control Pin for the Oscillator Section (1.8 V logic only). See REFCLK Input section for detailed
instructions.
This pin provides the connection for the external zero compensation network of the REFCLK
multiplier’s PLL loop filter. The network varies based on the multiplication value in the PLL loop.
See Table 4 for details.
Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.
DAC Output. Should be biased through a resistor to AVDD, not AGND.
DAC Band Gap Decoupling Pin. A 0.1 μF capacitor to AGND is recommended.
A resistor (3.92 kΩ nominal) connected from AGND to DAC_RSET establishes the reference
current for the DAC. See equation in DAC Output section.
Comparator Output.
Comparator Input.
Rev. B | Page 8 of 40
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