AD9953ASV Ver la hoja de datos (PDF) - Analog Devices
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AD9953ASV Datasheet PDF : 42 Pages
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PRELIMINARY TECHNICAL DATA
AD9953
GENERAL DESCRIPTION
The AD9953 is a Direct Digital Synthesizer (DDS) featuring a
14-bit DAC operating up to 400MSPS. The AD9953 uses
advanced DDS technology, coupled with an internal high-speed,
high performance D/A converter to form a digitally-
programmable, complete high-frequency synthesizer capable of
generating a frequency-agile analog output sinusoidal waveform
at up to 200 MHz. The AD9953 is designed to provide fast
frequency hopping and fine tuning resolution (32-bit frequency
tuning word). The frequency tuning and control words are loaded
into the AD9953 via a serial I/O port. The AD9953 includes an
integrated 1024x32 Static RAM to support flexible frequency
sweep capability in several modes.
The AD9953 is specified to operate over the extended industrial
temperature range of -40° to +85°C.
ABSOLUTE MAXIMUM RATINGS1
Maximum Junction Temp. ............................. +150 °C
Vs ............................................................................ +4 V
Digital Input Voltage............................... -0.7 V to +Vs
Digital Output Current ....................................... 5 mA
Storage Temperature ................................... -65 °C to +150 °C
Operating Temp. ............................................ -40 °C to +85 °C
Lead Temp. (10 sec. soldering) ................................... +300 °C
θJA .................................................................................. 38°C/W
θJC
15 °C/W
* Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability
of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied.
Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
CONTENTS
Functional Block Diagram
GENERAL DESCRIPTION
AD9954 PRELIMINARY ELECTRICAL SPECIFICATIONS
AD9953 Pinmap
Pin Name
I/O
Component Blocks
DDS Core
Phase Truncation
Clock Input
Phase Locked Loop (PLL)
DAC Output
Serial IO Port
Register Maps and Descriptions
Control Register Bit Descriptions
Control Function Register #1 (CFR1)
Control Function Register #2 (CFR2)
Control Function Register #2 (CFR2)
Other Register Descriptions
Amplitude Scale Factor (ASF)
Amplitude Ramp Rate (ARR)
Frequency Tuning Word 0 (FTW0)
Phase Offset Word (POW)
REV. PrB 1/30/03
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Analog Devices, Inc.
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