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AD8382ACP

High Performance 12-Bit, 6-Channel Output, Decimating LCD DecDriver®

Analog Devices 

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

AD8382

DB0 1

DB1 2

DB2 3

DB3 4

DB4 5

DB5 6

DB6 7

DB7 8

DB8 9

DB9 10

DB10 11

DB11 12

PIN 1

INDICATOR

AD8382

TOP VIEW

(Not to Scale)

36 VID0

35 AVCC0,1

34 VID1

33 AGND1,2

32 VID2

31 AVCC2,3

30 VID3

29 AGND3,4

28 VID4

27 AVCC4,5

26 VID5

25 AGND5

NC = NO CONNECT

Figure 6. 48-Lead LFCSP, 7 mm × 7 mm Package

Table 4. Pin Function Descriptions

Mnemonic

DB(0:11)

CLK

STSQ

Function

Data Input

Clock

Start Sequence

R/L

Right/Left Select

E/O

Even/Odd Select

XFR

VID0–VID5

V1,V2

VREFHI,

VREFLO

INV

DVCC

DGND

AVCCx

AGNDx

BYP

STBY

Data Transfer

Analog Outputs

Reference Voltages

Full-Scale References

Invert

Digital Power Supply

Digital Supply Return

Analog Power Supplies

Analog Supply Returns

Bypass

Standby

Description

12-Bit Data Input. MSB = DB(11).

Clock Input.

A new data loading sequence begins on the rising edge of CLK when this input was HIGH on

the preceding rising edge of CLK and the E/O input is held HIGH. A new data loading sequence

begins on the falling edge of CLK when this input was HIGH on the preceding falling edge of

CLK and the E/O input is held LOW.

A new data loading sequence begins on the left, with Channel 0, when this input is LOW, and

on the right, with Channel 5, when this input is HIGH.

The active CLK edge is the rising edge when this input is held HIGH and the falling edge when

this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is

HIGH and on the falling edges when this input is LOW.

Data is transferred to the outputs on the immediately following falling edge of CLK when this

input is HIGH on the rising edge of CLK.

These pins are directly connected to the analog inputs of the LCD panel.

The voltages applied between these pins and AGND set the reference levels of the analog

outputs.

The voltage applied between these pins sets the full-scale output voltage.

When this pin is HIGH, the analog output voltages are at or above V2. When this pin is LOW,

the analog output voltages are at or below V1.

Digital Power Supply.

This pin is normally connected to the analog ground plane.

Analog Power Supplies.

Analog Supply Returns.

A 0.1 µF capacitor connected between this pin and AGND ensures optimum settling time.

When HIGH, the internal circuits are debiased and the power dissipation drops to a minimum.

Rev. 0 | Page 7 of 24

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