PCA9511ADR2G Ver la hoja de datos (PDF) - ON Semiconductor

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PCA9511ADR2G

Hot Swappable I2C-Bus and SMBus Bus Buffer

ON Semiconductor 

PCA9511A

at its initial slew rate only until it is just above the first pin

voltage, then they will both continue down at the slew rate

of the first.

Once both sides are LOW, they will remain LOW until all

the external drivers have stopped driving LOWs. If both

sides are being driven LOW to the same value, for instance,

10 mV by external drivers, which is the case for clock

stretching and is typically the case for acknowledge, and one

side external driver stops driving that pin will rise until the

internal driver pulls it down to the offset voltage. When the

last external driver stops driving a LOW, that pin will rise up

and settle out just above the other pin, as both rise together

with a slew rate determined by the internal slew rate control

and the RC time constant. As long as the slew rate is at least

1.25 V/ms, when the pin voltage exceeds 0.6 V for the

PCA9511A, the rise time accelerator’s circuits are turned on

and the pull−down driver is turned off.

Maximum Number of Devices in Series

Each buffer adds about 0.1 V dynamic level offset at 25_C

with the offset larger at higher temperatures. Maximum

offset (Voffset) is 0.150 V with a 10 kW pull−up resistor. The

LOW level at the signal origination end (master) is

dependent upon the load, and the only specification point is

that the I2C−bus specification of 3 mA will produce VOL <

0.4 V, although if lightly loaded, the VOL may be ~0.1 V.

Assuming VOL = 0.1 V and Voffset = 0.1 V, the level after four

buffers would be 0.5 V, which is only about 0.1 V below the

threshold of the rising edge accelerator (about 0.6 V). With

great care, a system with four buffers may work, but as the

VOL moves up from 0.1 V, noise or bounces on the line will

result in firing the rising edge accelerator, thus introducing

false clock edges. Generally, it is recommended to limit the

number of buffers in series to two, and to keep the load light

to minimize the offset.

The PCA9510A (rise time accelerator is permanently

disabled) and the PCA9512A (rise time accelerator can be

turned off) are a little different with the rise time accelerator

turned off because the rise time accelerator will not pull the

node up, but the same logic that turns on the accelerator turns

the pull−down off. If the VIL is above ~0.6 V and a rising

edge is detected, the pull−down will turn off and will not turn

back on until a falling edge is detected.

Figure 3. System with 3 Buffers Connected to Common Node

Consider a system with three buffers connected to a

common node and communication between the Master and

Slave B that are connected at either end of buffer A and

buffer B in series as shown in Figure 3. Consider if the VOL

at the input of buffer A is 0.3 V and the VOL of Slave B (when

acknowledging) is 0.4 V, with the direction changing from

Master to Slave B and then from Slave B to Master. Before

the direction change, you would observe VIL at the input of

buffer A of 0.3 V and its output, the common node, is ~0.4

V. The output of buffer B and buffer C would be ~0.5 V, but

Slave B is driving 0.4 V, so the voltage at Slave B is 0.4 V.

The output of buffer C is ~0.5 V. When the Master

pull−down turns off, the input of buffer A rises and so does

its output, the common node, because it is the only part

driving the node. The common node will rise to 0.5 V before

buffer B’s output turns on, if the pull−up is strong, the node

may bounce. If the bounce goes above the threshold for the

rising edge accelerator ~0.6 V, the accelerators on both

buffer A and buffer C will fire contending with the output of

buffer B. The node on the input of buffer A will go HIGH as

will the input node of buffer C. After the common node

voltage is stable for a while, the rising edge accelerators will

turn off and the common node will return to ~0.5 V because

the buffer B is still on. The voltage at both the Master and

Slave C nodes would then fall to ~0.6 V until Slave B turned

off. This would not cause a failure on the data line as long as

the return to 0.5 V on the common node (~0.6 V at the Master

and Slave C) occurred before the data setup time. If this were

the SCL line, the parts on buffer A and buffer C would see

a false clock rather than a stretched clock, which would

cause a system error.

Propagation Delays

The delay for a rising edge is determined by the combined

pull−up current from the bus resistors and the rise time

accelerator current source and the effective capacitance on

the lines. If the pull−up currents are the same, any difference

in rise time is directly proportional to the difference in

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