EVAL-AD1940AZ Ver la hoja de datos (PDF) - Analog Devices
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EVAL-AD1940AZ Datasheet PDF : 36 Pages
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SPECIFICATIONS
Test conditions, unless otherwise noted.
Table 1.
Parameter
Supply Voltage (VDD)
PLL Voltage (PLL_VDD)
Output Voltage (ODVDD)
INVDD Voltage
Ambient Temperature
Master Clock Input
Load Capacitance
Load Current
Input Voltage, HI
Input Voltage, LO
Conditions
2.5 V
2.5 V
5.0 V
5.0 V
25°C
3.072 MHz, 64 × fs mode
50 pF
±1 mA
2.4 V
0.8 V
AD1940/AD1941
DIGITAL I/O
VDD = 2.25 V to 2.75 V. Specifications measured across −40°C to 125°C (case).
Table 2.
Parameter
Input Voltage, HI (VIH)
Input Voltage, LO (VIL)
Input Leakage (IIH)
Input Leakage (IIL)
High Level Output Voltage (VOH)
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Low Level Output Voltage (VOL)
Input Capacitance
Comments
Min
Max
Unit
2.1
V
0.8
V
10
μA
10
μA
ODVDD = 4.5 V, IOH = 1 mA
3.9
V
ODVDD = 3.0 V, IOH = 1 mA
2.6
V
ODVDD = 4.5 V, IOL = 1 mA1
0.4
V
ODVDD = 3.0 V, IOL = 1 mA1
0.3
V
5
pF
1 SDA is measured with a 3 mA sink current.
POWER
Table 3.
Parameter
SUPPLIES
Voltage
Digital Current
PLL Current
Digital Current, Reset
PLL Current, Reset
DISSIPATION
Operation, All Supplies
Reset, All Supplies
Min
Typ
Max1 Unit
2.25
2.5
2.75 V
92
1552 mA
3.5
8
mA
4.53
133
mA
3
8.5
mA
238.8
mW
10.8
mW
1 Maximum specifications are measured across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V.
2 Measurement running a typical large program that writes to all 16 outputs with 0 dB digital sine waves applied to all eight inputs. The end user’s program may differ.
3 The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.
Rev. B | Page 3 of 36
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