HSP43881/883 Ver la hoja de datos (PDF) - Intersil
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HSP43881/883 Datasheet PDF : 7 Pages
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HSP43881/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
NOTES
GROUP A
SUBGROUP
S
TEMPERATURE
(oC)
-25 (25.6MHz)
MIN
MAX
UNITS
Clock Period
Clock Low
Clock High
Input Setup
Input Hold
CLK to Coefficient
Output Delay
t CP
tCL
tCH
tIS
tIH
tODC
Note 5
9, 10, 11
-55 ≤ TA ≤ 125
39
-
ns
Note 5
9, 10, 11
-55 ≤ TA ≤ 125
16
-
ns
Note 5
9, 10, 11
-55 ≤ TA ≤ 125
16
-
ns
Note 5
9, 10, 11
-55 ≤ TA ≤ 125
17
-
ns
Note 5
9, 10, 11
-55 ≤ TA ≤ 125
0
-
ns
Note 5
9, 10, 11
-55 ≤ TA ≤ 125
-
20
ns
Output Enable Delay
CLK TO SUM
Output Delay
tOED
tODS
Note 5
9, 10, 11
-55 ≤ TA ≤ 125
-
15
ns
Note 5
9, 10, 11
-55 ≤ TA ≤ 125
-
25
ns
NOTE:
5. AC Testing: VCC - 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are
made at 1.5V for both a Logic “1” an”). CLK is driven at 4.0V and 0V and measured at 2.0V.
TABLE 3. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER
SYMBOL
TEST
CONDITIONS
NOTES
TEMP
(oC)
-25 (25.6MHz)
MIN MAX
UNITS
Input Capacitance
CIN
VCC = Open, f = 1MHz
6
All measurements are
referenced to device GND
TA = 25
-
15
pF
Output Capacitance
COUT
6
TA = 25
-
15
pF
Output Disable Delay
t ODD
6, 7
-55 ≤ TA ≤ 125
-
15
ns
Output Rise Time
t OR
6, 7
-55 ≤ TA ≤ 125
-
6
ns
Output Fall Time
t OF
6, 7
-55 ≤ TA ≤ 125
-
6
ns
NOTES:
6. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.
7. Loading is as specified in the test load circuit, CL = 40pF.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
-
PDA
100%
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
Group A
-
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C and D
Samples/5005
1, 7, 9
5
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